[time-nuts] Question about DDMTD deglitching

Bob Camp lists at rtty.us
Sat Feb 22 13:00:26 EST 2014


Hi

When you do any of these delay line based gizmos, you get some very strange outputs. Flip flops go metastable, edges don’t quite arrive in the right sequence. If all you do is look for solid ones or solid zeros you don’t get a lot of data. Counting the ones and counting zeros is another approach. 

They calibrate the devices by random pulses and then categorizing the result. By deciding that all buckets with the same number of 1’s and 0’s in them (plus some other stuff) are equal, they get more hits per bucket. That gives more data in less time. 

The implicit assumption is that buckets with equal 0’s and 1’s (and what ever else) are equal to each other time wise. Another related assumption is that buckets with fewer 0’s and more 1’s are slower (or faster depending on the structure) than ones with more 0’s. 

There apparently is some strong data somewhere suggesting that this is all true.

Bob

On Feb 22, 2014, at 12:30 PM, Robert Darby <bobdarby at triad.rr.com> wrote:

> In August 2011 there was a brief mention on Time-Nuts of DDMTD's which led me to The P. Moreira  and I. Darwazeh  paper "Digital femtosecond time difference circuit for CERN’s timing system".  I'm hoping that someone can explain one item mentioned in this paper for me.   For those not familiar with this work, it is part of a sub-nanosecond network synchronization scheme know as White Rabbit.
> 
> One of the elements of the DDMTD is a deglitching system and the authors describe three possible deglitching strategies.  The first two are quite straightforward but the third method  described as "Zero Count – counts the numbers of “1” and “0” and selects as the best edge the time position where the number of zeros is the same as the number of ones." seems totally ambiguous.  If I take the statement quite literally, there must be dozens or hundreds of times when the number of 1's and 0's in a glitch are equal.   Can anyone familiar with this work explain what I am missing? I realize that the answer to my question is probably at hand in the FPGA code but that's well beyond my pay grade.
> 
> This paper is available at:
> http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf
> A list of White Rabbit papers is available at:
> http://www.ohwr.org/projects/white-rabbit/wiki/WRpublications
> 
> Thanks,
> Bob Darby
> 
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