[time-nuts] 'CPLDs for clock dividers' Thread

[Ulrich Bangert]

John,

I have tried to incorporate the digital dividers of a linear phase
comparator into a CPLD. While it worked "in principle" as planned I had lots
of problems when the slopes of the input signals came close to each other,
this being due to

> >> CPLDs or FPGAs are neat because you can toss all sorts of stuff into 
> >> them. If you do that, you introduce opportunities for power supply 
> >> level noise coupling.

The power supply coupling may change the point of time when ONE slope
appears at the outpuit of the divider in dependence of when the SECOND slope
appears. Of couse this effect is not in the order of microseconds, not even
nanaoseconds but say a few hundred picoseconds and thus some orcders of
magnitude worse than phase comparator was expected to work. A "normal"
digital designer would not care about it only time nuts do.

> > I am working on a PLL design that uses the Lattice MX02-256 for the 
> > dividers and XOR phase detector.  I have not made any measurements on 
> > it yet but will report back when it happens.

A PLL design will give you much less trouble with the following
justification: The low pass filter following the XOR phase comparator must
have a cut off frequency that is suited to supress the XOR's output
frequency (double the PLL's frequency) well enough. ANY kind of disturbance
that is superimposed to the XOR's output (jitter, you name it) has basically
a higher frequency than the XOR's output itself. SO it will even be better
filtered out by the low pass filter. I have done some PLLs in CPLDs without
ever getting in trouble. Get yourself the data sheet of the AD9901
frequency/phase comparator. It will show you how to improve the simple XOR
with circuitry that makes the comparator also frequency dependend. With this
the lock-in range will be the same as the lock range, a feature that is not
common for XOR based PLLs.

Best regards
Ulrich



> -----Ursprungliche Nachricht-----
> Von: time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von John C. 
> Westmoreland, P.E.
> Gesendet: Montag, 6. Januar 2014 06:17
> An: Tom_Minnis at att.net; Discussion of precise time and 
> frequency measurement
> Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread
> 
> 
> Hello Tom,
> 
> Thanks for replying.  I will be interested to see what you 
> end up with for jitter, phase noise, and propagation delay; 
> to name a few.  Looks like an interesting part from the datasheet.
> 
> Thanks,
> John W.
> 
> 
> On Sun, Jan 5, 2014 at 8:29 PM, Tom Minnis <Tom_minnis at att.net> wrote:
> 
> > I am working on a PLL design that uses the Lattice MX02-256 for the 
> > dividers and XOR phase detector.  I have not made any 
> measurements on 
> > it yet but will report back when it happens.
> >
> >
> > On 1/5/2014 7:37 PM, Hal Murray wrote:
> >
> >> I was looking at the archives - what was the outcome of this:
> >>>
> >> What level of nuttiness are you interested in?
> >>
> >> CPLDs or FPGAs are neat because you can toss all sorts of 
> stuff into 
> >> them. If you do that, you introduce opportunities for power supply 
> >> level noise coupling.
> >>
> >> If you have something simple like a divide by 2 or divide 
> by 10 with 
> >> no other logic in the chip, I'd expect the output to be clean.  If 
> >> you want to do a divide by 2 AND 10, I'll bet you will see some 
> >> coupling.  (at least if you look hard enough)
> >>
> >> Fine print:
> >>    One buzzword to look for is SSO - Simultaneous 
> Switching Output.  
> >> The basic idea is that there is slight 
> inductance/resistance in the 
> >> power/ground connections and on chip power/ground 
> distribution.  If 2 
> >> signals switch at the same time, they share that and will 
> be slightly 
> >> slower than only one signal switching.
> >>
> >>    You will probably get better results if your output PIN 
> is next to 
> >> pwr/gnd pins.  (lower on-chip resistance)
> >>
> >>    You may be able to help things by setting up nearby pins as 
> >> outputs and wiring those pins to pwr/gnd and driving them with the 
> >> appropriate logic level.  The idea is to add semi-pwr pins.  The 
> >> resitance through the driver transistors is small enough 
> so that it 
> >> helps.
> >>   It would be fun to measure some of that stuff.
> >>
> >>
> >>
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