[time-nuts] 'CPLDs for clock dividers' Thread

Hal Murray hmurray at megapathdsl.net
Mon Jan 6 18:17:00 UTC 2014


vesoares at deea.isel.ipl.pt said:
> With respect to jitter does anyone compared the solutions using a PLL or DCM
>  on FPGAs for clock dividing? For instance, from 10 MHz to 44.1 kHz which
> would be the best option? Does a CPLD supersedes those FPGA functionalities
> for that kind of operation? 

If you read the fine print in the Xilinx data sheets for their FPGAs with 
DCMs you will see that they will be horrible for things like good phase 
noise.  They are using digital DLLs, delay locked loops, rather than analog 
PLLs.  It's a long string of buffers.  They tap off at the right place and 
jiggle the tap back and forth as needed.  That "jiggle" covers two things.  
One is the fractional tap to get the right frequency.  I'd expect the output 
to have spurs like a DDS.  The jiggle also gets adjusted to cover things like 
temperature shifts, so the spurs you see now may be different if you wait a 
few minutes.

If you don't use the DCM, I'd expect them to work reasonably well.  They 
probably have more logic than you need for a simple clock divider and you 
have to reload them at power up.


-- 
These are my opinions.  I hate spam.






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