[time-nuts] How to clock a Beaglebone Black from an external reference

[Simon Marsh]

Most processors can be clocked from a variety of sources and we know 
that with a bit of hacking it can be possible to connect them up to a 
time-nut-standard reference (either directly for simple microprocessors 
or with a synthesizer/pll).

The Beaglebone Black is my weapon of choice when it comes to embedded 
boards and being able to lock it to an external reference should give 
some obvious benefits, such as being a great NTP server (e.g. a more 
modern equivalent of the Soekris boards) to having access to a large 
number of timers & peripherals synchronised to the reference. The BBB 
requires a 24mhz clock to operate, so the end goal here will be to get 
it running from a 10mhz reference multiplied up by a PLL.

The TL;DR summary is that despite the scary amount of tiny surface mount 
components on the board, the modifications actually turned out to be 
quite simple and, on first look, the result is great performance.

So here's how to do it.

Modification Details

The BBB contains a TI Sitara AM3358 SoC and section 6.2 of the relevant 
datasheet (http://www.ti.com/lit/ds/symlink/am3358.pdf) details the 
various clocking options for the core. The key bit of information is 
that the core will automatically use an external crystal or an LVCMOS 
clock source and does not require any specific configuration to be made 
either way.

The schematic for the BBB is readily available 
(https://github.com/CircuitCo/BeagleBone-Black/blob/master/BBB_SCH.pdf) 
and the upper left corner of page 3 details how the crystal on the board 
is connected.

Together, the datasheet and schematic suggest that hooking up the BBB to 
an external LVCMOS source should be as easy as simply removing the 
existing crystal and attaching the source to OSC0_IN (pad 2 of the 
crystal). The crystal is marked as Y2, has a couple of supporting 
capacitors (C25 & C26), and an associated resistor (R17).

The crystal is nicely marked up on the board itself and is easy to spot. 
It's on the underside and attached are a couple of photos for reference. 
The photo is of a Rev C. Element 14 BBB; earlier revisions of the board 
have a different, large, black crystal but the board layout is the same.

The main risk with removing the crystal is the proximity of all the tiny 
surface mount parts, but it turned out to be very simple with a basic 
hot air gun and some tweezers. I also removed R17 (the spec of dust sat 
between C25 & C26), as the SoC datasheet stated OSC0_OUT should be left 
unconnected. The whole process was suprisingly easy, took less than a 
minute and I didn't need to resort to any magnifying aids.

The location of C25 & C26 help understand the orientation of the 
crystal, the external source needs to be attached to the pad nearest 
C25. This is the left hand pad in the photos. After the crystal has been 
removed, the remaining pads are nice and big making soldering of a coax 
cable straightforward.

A final photo shows the crystal and R17 removed, and with coax attached.

Test & Performance

In order to check the change was working, I clocked the BBB using a 
MicroCrystal OCXO connected to a cheap PLL-on-a-chip. The PLL I used has 
woefully few specs with regards to jitter etc, but had the virtue of 
being to hand, operated at 3.3v and directly provided a 2.4 multiplier 
to get 24mhz needed for the BBB. The BBB was connected to an adafruit 
GPS breakout and the lot was left out overnight on an open desk running 
NTP and using the gps as a PPS source.

I'd intended to provide some nice graphs from NTP, but in practice the 
NTP jitter flatlined at 4us and the offset all night was practically 
flat as well, showing only occasional variation with maximums of +- 2us. 
This was great from a performance view, suggesting performance is better 
than NTP can report, but does make for some dull graphs.

The frequency plot was barely more interesting but is attached; the 
scale is ppm and shows a drift of less than 0.1 ppm over 12 hours; this 
I think is consistent with the spec of the OCXO. Note the room is not 
air conditioned and my heating comes on between 6am and 7am; there is a 
nice lack of impact, as you would hope. For comparison, my RasPI NTP 
server varies about 1ppm, with offsets of +- 50us corresponding to 
temperature variations.

Overall, this was quite a trivial test but nicely succesful.

Internally the BBB has quite a few different clock domains so, longer 
term, it will be interesting to see if the impact of the SoC internal 
PLLs can be measured. Whilst not an issue for something as high level as 
NTP, the PLLs will determine the detail of how the reference stability 
transfers to peripherals like the BBB timers and PRU.

Cheers



Simon
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