[time-nuts] Time tagging fpga

[Bob Camp]

Hi

I believe the DMTD mentioned is the one done by Bill Riley. It’s at:

http://www.wriley.com/A%20Small%20DMTD%20System.pdf

That paper has way more info on the device and it’s signal processing than is worth going into on the list. There has been some discussion about the limiters used here on the list. I’d offer the quick summary of: they are adequate for the task. 

The active filtering ahead of the limiters is specific to a pre-defined range of offset frequencies / beat notes. It covers the ones most people use. 

The performance data shown on the site pretty well demonstrates that the box is up to any task a normal Time Nut would use it for. Those with multiple optical ion trap standards in the basement may need to tweak it a little :)

Bob

> On Nov 23, 2014, at 9:57 AM, Anders Wallin <anders.e.e.wallin at gmail.com> wrote:
> 
>> 
>> Anders,
>> The counter runs on a Pipistrello.  I looked at the information on the web
>> about time taggers before starting.  I decided to try an oversampling
>> scheme described by a group of  Italian? physicists for a multichannel time
>> tagging instrument.  They used 4x oversampling.  My version is crude; it
>> uses the 50 MHz on-board clock but of course could use an external clock
>> source.  The clock is multiplied to 1 GHz and then divided into four 125 Hz
>> clocks phased 45 degrees apart.  There is a fifth 125 MHz clock at 0 phase
>> for the main counter and external interface.
>> There are four channels, each with 3 bits for value and a forth bit
>> indicating an event.  The sixteen bits are followed by a 48 bit counter
>> value.
>> 
> 
> what, if any, signal conditioning do you have between the DMTD output and
> the FPGA? I was thinking about copying the CERN DIO design which looks like
> this:
> http://ibin.co/1iEwLuAUQYJ4
> it has a fuse, a resistor to set the input impedance, protection diodes,
> and an ADCMP604 that outputs an LVDS pair to the FPGA.
> 
> The CERN design is for a 125 MHz clock. What would be the preferred way to
> generate this for the Pipistrello, with an optional 10MHz reference input?
> OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a
> tested circuit that autodetects the external 10MHz and can switch between
> the OCXO and ext-ref?
> 
> 
> 
>> This yields 1 ns resolution (bin size) but the bins sizes are certainly
>> not all equal.  I have few means to check the accuracy but for my purposes
>> (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more
>> accurate than I need.  I have experimented with .5 ns bin sizes, also using
>> the 8x oversampling with a 250 MHz clock.  To keep the backend 125 MHz
>> structure I used a two phase multiplexer to combine two successive samples.
>> This runs but is not reliable and needs further work before it's useful.
>> 
> 
> Did you post the schematic for your DMTD?
> Many of the time-to-digital papers calibrate the bin-width by collecting
> time-stamps from an asynchronous pulse-source. If the bins are equal you
> should get a flat histogram. Some use a ring-oscillator on the fpga for
> generating the asynchronous hits.
> 
> 
> Anders
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