[time-nuts] Clock level conversion 5V -> 3.3V
vesoares at deea.isel.ipl.pt
Wed Oct 1 04:47:45 EDT 2014
More than a matter of personal taste avoiding a resistive divider using a
active circuit you could benefit from its low output impedance. With a
resistive divider there could be some issues in terms of impedance matching
when a load it is present but as been said it all depends on how good that
level translation should be.
----- Original Message -----
From: "Hal Murray" <hmurray at megapathdsl.net>
To: "Discussion of precise time and frequency measurement"
<time-nuts at febo.com>
Cc: <hmurray at megapathdsl.net>
Sent: Wednesday, October 01, 2014 4:10 AM
Subject: Re: [time-nuts] Clock level conversion 5V -> 3.3V
> vesoares at deea.isel.ipl.pt said:
>> I would suggest some 3.3V logic (inverter) gate with 5V tolerant inputs
>> from Little Logic TI portfolio. There are buffered and unbuffered gate
> What's the advantage of a chip over a pair of resistors?
> haunma at keteu.org said:
>> I have seen a resistive divider used in a similar application, but
>> if I could save the couple dozen mA they were spending.
> Power might be one. If it's a long enough run that you need a
> then the power doesn't cost anything extra. If it's only a few inches,
> can use higher values of resistance to save the power.
> For a given value of resistance and a specific chip, there should be some
> crossover frequency where the power of the chip matches the power of the
> resistors. It might be fun to play with the numbers.
> These are my opinions. I hate spam.
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