[time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop

[Bruce Griffiths]

The use of a synchroniser loses no information apart from fine details about the metastability response of the sampling flipflop. With a 10Hz offset and a 10MHz clock the sampling resolution is 100fs with the phase difference between the flipflop clock and data input transitions changing monotonically by 100fs between successive active clock transitions. Phase noise/jitter between the flipflop and data input transitions will typically result in a burst of state transitions at the synchroniser output rather than a single transition when the active clock transition and a data transition coincide..

Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter.

Bruce