[time-nuts] BBB DDMTD - analysis

Hal Murray hmurray at megapathdsl.net
Thu Oct 30 14:13:34 EDT 2014


subscriptions at burble.com said:
> In an effort to understand which component was responsible for my ~17us
> spikes I decided to go back to basics with just a single DFlop (AC74) on  a
> breadboard; no BBB, just a couple of oscillators driving the data and  clock
> pins ...

I don't know what the problem is, but metastability won't cause numbers like 
"~17us".

With classic metastability, there are 2 parameters.  One is the probability 
of going metastable.  That's the width of the window on setup time where bad 
things happen.  The other is how long it takes to return to a valid logic 
level, the gain-bandwidth around the feedback loop in the FF.

One way of describing metastability is that if you don't meet the setup and 
hold times, it won't meet the clock-out time.  If you make a histogram of the 
measured clock-out times, it decays exponentially - straight line on a log 
plot.

Metastability scales with the speed of the logic family.  If you switch to a 
slower part, the histogram should shift to the right.

Also, 17 microseconds is huge.  Microseconds.  Right?

There are several good scope pictures here:
  http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm



-- 
These are my opinions.  I hate spam.






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