[time-nuts] Ultra High Stability Time Base Options for 53132A

[John Miles]

>The faster the comparator, the greater its analog bandwidth.
>Thus there is more total noise to cause jitter.  The DC to
>daylight comparator is the opposite of the John Dick (JPL)
>paper on zero crossing detectors in PTTI around 1990.  John
>teaches that you use the MINIMUM bandwidth amplifier to
>square up a sine wave.

Although you hear it a lot, I'm not so sure of the generality of this statement.  It would make sense if you were talking about a sampling process where noise from the entire system bandwidth is aliased irreversibly into the output signal, but I don't see a compelling reason to think of a ZCD that way.  It's true that saturated logic is quieter than unsaturated logic, but during the critical zero crossing time, is it really saturated?  If the device is faster than the input signal, the answer is a definite "No," and that's where I think the conventional wisdom about fast comparators being bad for jitter comes from.  They aren't contributing more jitter, they're just failing to clean up the input jitter during the transition time.  

All other things being equal, it's desirable to minimize the time spent in that region of the waveform.  It doesn't necessarily hurt to choose a faster logic family, as long as the process noise and device gain are otherwise compatible with the decision.  Random jitter on the 7.5 GHz ADCLK905 is specified at around 60 femtoseconds, after all.  A residual PN test at 10 MHz on an ADCLK905 ends up at around -135 dBc/Hz at 1 Hz just like many other slower comparators, a figure that's good for 1s ADEVs in the E-14s (see http://www.ke5fx.com/ADCLK905_ADEV.png and http://www.ke5fx.com/ADCLK905_PN.png).  

At lower carrier frequencies, the ADCLK905's apparent jitter is worse because the low slew rate of the input signal gives its open-loop gain more time to influence the outcome.  But it wouldn't be significantly better if the ADCLK905's bandwidth were a thousand times lower.  Of course, when the input signal is *much* slower, as in the JPL paper, a multistage shaper with optimized bandwidth and gain allocation is helpful.  But their situation at 1 Hz is not directly applicable at 5/10 MHz.  An obsessive focus on bandwidth here is just going to make the phase tempco worse without improving the jitter.

> BTW: If anyone here has any good text to read on oscillator design,
> please let me know. I'm collecting those :-)

In addition to the ones Rick mentioned, you might look into Enrico Rubiola and Jeremy Everard.

-- john, KE5FX
Miles Design LLC