[time-nuts] GPSDO and oscillator steering - EFC vs DDS schemes?

Alexander Pummer alexpcs at ieee.org
Wed Dec 9 03:58:30 UTC 2015


Bar Giora Goldberg wrote a book on DDS Digital Frequency Synthesis 
Demystified 
<http://www.amazon.com/Frequency-Synthesis-Demystified-Bar-Giora-Goldberg/dp/1878707477#>see 
here: 
http://www.amazon.com/Frequency-Synthesis-Demystified-Bar-Giora-Goldberg/dp/1878707477
[· In-depth coverage of modern digital implementations of frequency 
synthesis architectures
· Numerous design examples drawn from actual engineering projects
· The accompanying CD includes digital frequency synthesis design tools 
and an electronic version of the book]
Hi was the chef technologist of  Sciteq, that company made the first 
usable DDS devices.
73
KJ6UHN
Alex


On 12/8/2015 4:00 PM, Attila Kinali wrote:
> On Tue, 8 Dec 2015 10:09:44 -0800
> Jim Lux <jimlux at earthlink.net> wrote:
>
>>> What puzzled me is, why this has not been used more often to correct
>>> the frequency of OCXOs instead of using some DAC-to-EFC scheme?
>> Heritage... if you have a design that works, and there's a lot of them
>> in the field, and the idiosyncracies are well known and understood, then
>> one tends to stay with the old design.
> That might be an explanation.
>
>> DDS are "brand new", at least in terms of generating low spurs, etc.
>> The idiosyncracies are not as well understood.
> Well, Rick's paper is already 20 years old. There has been lots of
> discussion of DDS in the radio community and I think that community
> has a lot of knowledge of the idiosyncracies of DDS. I'm not sure
> how it works for the  time and frequency control community, though.
>
>> I think also the power consumption might be an issue.  Most good DDS
>> burn a lot of power, compared to a DAC.
> Compared to the 1-5W steady state of an OCXO?
> But yes, the circuit would probably need something in the range of 2-3W.
>   
>> There's also systems that depend on smooth sweeps without steps (yes,
>> one can design a DDS with a digital ramp generator driving the increment
>> in a phase accumulator to get arbitrarily smooth sweeps, but the "off
>> the shelf" parts don't do this)
> I might be naive, but I would have used an small FPGA with EEPROM cells
> (like the Lattice ICE or the Altera MAX) and build an DDS by hand that
> is tailored for exactly that purpose (to get minimal spurs), add an
> 10bit DAC, combine everything with an 60-100MHz VCXO that is PLL-locked to
> the 10MHz input. Well, actually the VCXO might not even be necessary,
> if the FPGA internal PLL is not too noisy, there is some heavy "damping"
> of the noise through the divider stages anyways.
>
>
>> I don't think parts cost is a big driver.
>
> Unless you are a hobbyist.
>
>
> 			Attila Kinali
>




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