[time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

Bob Camp kb8tq at n1k.org
Mon Dec 21 19:56:50 EST 2015


To go through the whole deal a step at a time *assuming* that broadband noise is the only issue:

-147 dbm noise per Hz
+10 dbm signal

=> -157 dbc / Hz

half to AM, half to PM

=> -160 dbc / Hz

ssb is already taken care of (noise on both sides if it’s broadband)

=> -160 dbc / Hz 

Now, assuming you have a modulation on the edge due to low frequency noise:

-147 dbm noise per Hz
+10 dbm signal 
+0 conversion gain (might be less, rarely is more)

=> -157 dbc / Hz
It all may go to PM so

=> -157 dbc / Hz

It’s DSB (sidebands are coherent) modulation so 

=> -151 dbc / Hz

You could easily say that all of the stuff after the conversion gain number is just messing around. 
That would indeed be correct. All that has been done is to calculate a conversion gain for low 
frequency noise to PM as read by a phase noise test set. The main point is to illustrate that you 
may be *more* sensitive to low frequency noise than you might think. 


Biased CMOS gates are looking better and better … -175 dbc / Hz floor with a 7 dbm input …. :)


> On Dec 21, 2015, at 3:05 PM, Anders Wallin <anders.e.e.wallin at gmail.com> wrote:
>>> AD8055 in non-inverting circuit with 1+2k7/2k7 gain has 9.6 nV/sqrt(Hz)
>>> input-referred voltage noise PSD (if I calculated correctly..)
>> With +10dBm input the corresponding SSB PN floor should be  around
>> -163dBc/Hz.
> HI,
> How is that calculated? I only get this far:
> 9.6nV/sqrt(Hz) into a 50R load is 1.8e-18 W/Hz or -147.3 dBm/Hz
> what then? split half-and-half into AM and PN, and how to relate that to
> the carrier power +10dBm?
> thanks,
> Anders
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