[time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Dec 22 19:07:45 UTC 2015


Thanks, driving the input with a low PN OCXO is probably the difference, John 
Miles used an HP8642 - not quite as low PN.
The PN test set is supposed to reject the source PN as it drives both inputs 
of the PN test set. However this rejection isn't perfect.
I'll try driving a 74AC04 input directly (I have sufficient signal level for 
this at the output of various low PN amplifiers). I'll also see if I can just 
measure the output of a single gate using a pair of low PN amps to drive the 
Timepod Channel0 and Channel2 inputs separately..

Deuterating the chip apparently reduces flicker noise more effectively than 
simply using Hydrogen to terminate dangling Si bonds at the oxide interface.
However I guess there's no easy way to determine if the chip was soaked in 
hydrogen or deuterium?? Perhaps baking the packaged chip in deuterium might 
help if the passivation and package are sufficiently permeable.

Bruce

On Tuesday, December 22, 2015 07:49:42 AM Bob Camp wrote:
> Hi
> 
> To be very specific about the floor on the gates (as measured with a
> TimePod):
> 
> 1) Clean 5.5V supply (max the part can rationally take).
> 2) Input signal L network transformed to just below the protection diode
> threshold (roughly 6V p-p) 3) Input signal to the power splitter is from an
> OCXO so it’s pretty clean and does not have a lot of “junk” on it. 4)
> Output is Tee network matched off of a pair of gates in parallel 5) Power
> supply is clean, but nothing special (LT1764).
> 
> I believe there are plots in the archives.
> 
> Bob
> 
> > On Dec 21, 2015, at 10:20 PM, Bruce Griffiths <bruce.griffiths at xtra.co.nz>
> > wrote:
> > 
> > Do those modern CMOS gates use deuterated wafers?I've not found any
> > measurements of the PN of modern CMOS gates.The measurements of devices
> > like the venerable 74AC04 indicate a PN floor around 10dBc/Hz worse than
> > that. Bruce
> > 
> >    On Tuesday, 22 December 2015 3:00 PM, Bob Camp <kb8tq at n1k.org> wrote:
> > Hi
> > 
> > To go through the whole deal a step at a time *assuming* that broadband
> > noise is the only issue:
> > 
> > -147 dbm noise per Hz
> > +10 dbm signal
> > 
> > => -157 dbc / Hz
> > 
> > half to AM, half to PM
> > 
> > => -160 dbc / Hz
> > 
> > ssb is already taken care of (noise on both sides if it’s broadband)
> > 
> > => -160 dbc / Hz
> > 
> > Now, assuming you have a modulation on the edge due to low frequency
> > noise:
> > 
> > -147 dbm noise per Hz
> > +10 dbm signal
> > +0 conversion gain (might be less, rarely is more)
> > 
> > => -157 dbc / Hz
> > 
> > It all may go to PM so
> > 
> > => -157 dbc / Hz
> > 
> > It’s DSB (sidebands are coherent) modulation so
> > 
> > => -151 dbc / Hz
> > 
> > You could easily say that all of the stuff after the conversion gain
> > number is just messing around. That would indeed be correct. All that has
> > been done is to calculate a conversion gain for low frequency noise to PM
> > as read by a phase noise test set. The main point is to illustrate that
> > you may be *more* sensitive to low frequency noise than you might think.
> > 
> > =====
> > 
> > Biased CMOS gates are looking better and better … -175 dbc / Hz floor with
> > a 7 dbm input …. :)
> > 
> > Bob
> > 
> >> On Dec 21, 2015, at 3:05 PM, Anders Wallin <anders.e.e.wallin at gmail.com> 
wrote:
> >>>> AD8055 in non-inverting circuit with 1+2k7/2k7 gain has 9.6 nV/sqrt(Hz)
> >>>> input-referred voltage noise PSD (if I calculated correctly..)
> >>> 
> >>> With +10dBm input the corresponding SSB PN floor should be  around
> >>> -163dBc/Hz.
> >> 
> >> HI,
> >> How is that calculated? I only get this far:
> >> 9.6nV/sqrt(Hz) into a 50R load is 1.8e-18 W/Hz or -147.3 dBm/Hz
> >> 
> >> what then? split half-and-half into AM and PN, and how to relate that to
> >> the carrier power +10dBm?
> >> 
> >> thanks,
> >> Anders
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