[time-nuts] 5>10 doubler

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Feb 3 05:30:38 UTC 2015


Whilst input frequency related spurs can be significantly reduced with a 
suitable filter incorporating a sufficient number of series tuned traps plus 
a low pass filter, phase noise once incurred cannot be reduced by such 
means.
The ultimate measure of performance of the phase noise performance of a 
frequency doubler is the input referred residual phase noise both for the 
noise floor and the flicker phase regions.
The Wenzel JFET frequency doubler implementation (based on the NIST 
design) has a specified input referred residual phase noise of
-155dBc/Hz @ 10Hz
-178dBc/Hz @100kHz.
for a 5MHz input signal. 
http://www.wenzel.com/wp-content/uploads/LNHD.pdf

A BJT variant of the same circuit has an input referred residual phase noise 
for a 5MHz input
-159dBc/Hz @ 10Hz offset
-180dBc/Hz @ 100KHz offset
If I have interpreted Adrian's measurements correctly see:
http://www.timeok.it/files/high_performance_frequency_doublerv13.pdf.

It would be interesting to compare these figures with the measured 
residual phase noise of other frequency doublers such as Gerard's JFET 
doubler using BF862's and the proposed near class A JFET based 
frequency doubler.

Bruce 

 
On Tuesday, January 27, 2015 02:25:54 PM Charles Steinmetz wrote:
> Andrea wrote:
> >Now I have some 5MHz DOCXO. I have started to experiment with them
> >and I would like to build a frequency doubler.
> >
> >      *   *   *
> >
> >By the way, I see that really many of the 10MHz reference out there, 
are in
> >effect doubled 5MHz ones so build a doubler seems reasonable for me.
> 
> One thing to watch for is the 5MHz leakage component.  If you are
> going to use the 10MHz standard for time-nuts experiments, the 5MHz
> component needs to be WAY down (< -80dBc) or you will get funny
> periodic ripples in stability plots.  Despite having two 5MHz traps,
> one recently published design suppresses the 5MHz component only
> about 52dB below the 10MHz output, and the 20MHz and 30MHz 
components
> are also only -50 to -55dB.
> 
> For this reason (and some others, see discussions over the last
> several months in the archives) I prefer a doubler built with a
> quadrature hybrid coupler and a balanced mixer.  There is a write-up 
here:
> 
> 
<http://www.ko4bb.com/manuals/download.php?file=02_GPS_Timing/4_App_
Notes_an
> d_Articles/Frequency_doubler_quadrature_DBM.pdf>
> 
> I recently revived an old, stalled project to develop a JFET
> push-push doubler for use at 5MHz (see schematic below).
> 
> FETs with very high transconductance and very small pinchoff voltage
> (what a tube designer would call a "sharp cutoff" characteristic)
> (e.g., 2SK369, BF862, etc.) are attractive on first look because they
> can operate with lower conversion loss or even some conversion
> gain.  However, they are not well suited for doubler duty for two
> reasons: (i) their characteristics have a very short range of
> 2nd-order curvature, so in order to keep noise down they must be
> driven into regions of higher-order distortion and therefore generate
> lots of spurious energy; and (ii) they are devilishly hard to match
> well enough to suppress the input frequency feedthrough.  Note that
> you also need to put enough voltage on the FET drains to get them
> well into the saturation region -- a Vcc of 5v is not enough.  Again,
> the penalty is lots of spurious energy.  So, the lower conversion
> loss of sharp-cutoff FETs is not the benefit it might at first appear
> to be -- it is much easier to add gain after the doubler than to
> remove unwanted spurious mixing products.
> 
> The design below uses medium-cutoff FETs and a Vcc of 15v (I found
> that J111 and J310 work best and can be matched sufficiently with a
> one-point match; 2N4416 and others also work, but are fussier and
> would benefit from a 2- or 3-point match).  At an input of 500mVrms,
> their long 2nd-order characteristic is used efficiently to generate
> 10MHz with relatively little spurious energy.
> 
> I had no problem finding one or more FET pairs matched to within 1mV,
> given 20 devices from the same lot (YMMV).  With properly adjusted
> traps at 5, 20, and 30MHz, all spurious responses were below
> -80dBc.  The inductors can be commercial RF parts with Q of 200 or so
> (I used some high-quality through-hole RF inductors I had on hand --
> I doubt any SMD inductors will work).  The trap capacitors should be
> C0G/NP0 ceramics for the bulk of the capacitance, plus very small
> trimmers (I used 27pF, 27pF, and 100pF plus 0.2--6pF glass piston
> trimmers).  I wound the two transformers on Mix-61 toroid cores (each
> winding is 20 turns on a FT37-61 core -- the inductance is a little
> lower than called out).  Mini-Circuits parts (or equivalents) may also 
work.
> 
> Best regards,
> 
> Charles




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