[time-nuts] homebrew counter new board test result

Li Ang lllaaa at gmail.com
Fri Feb 27 11:31:26 UTC 2015


 Hi
   Thanks about the explanation on hysteresis and comparator.
   The PM6685(http://assets.fluke.com/manuals/PM6685__smeng0000.pdf )
is using 74ALS176 as the frontend for REF channel.
So
I tried that on the previous board. The performance is better with
74ALS176+74LVC2G14 than MC100LVELT22 at the sin wave input condition.
    Since the stdev has reached the spec of TDC chip, I need to do
some more experiments with these chips next.
    There are some questions I want to ask:
1) Does the trigger interval need to be very accurate? Now I am using
software scheduler to generate the interval, it might vary few ms.
2) Does any one have the test data of 12 digit/s counter when DUT=REF?
I want to know the gap between mine and a  commercial counter.


Thanks

Li Ang

2015-02-27 4:30 GMT+08:00 Charles Steinmetz <csteinmetz at yandex.com>:

> Magnus wrote:
>
>  A bit of hysteresis can help to avoid flipping back, but considering the
>> type of signal, it passes the mid-point (0 V) at highest slew-rate, so
>> there is very little risk of flipping back and fourth in the first
>> place, so hysteresis may not even be needed.
>>
>
> A 1 Vrms, 10MHz sine wave has a zero-cross slew rate of 88v/uS (88mV/nS).
> One would think that would be enough to avoid indecision in a comparator
> with 5-10nS of propagation delay.  However, the LT1016 (10nS) is prone to
> jitter problems when operating as a ZCD with such a signal, and external
> hysteresis does not help much because it is delayed by 10nS.  (The problem
> appears to be that the front end has some indecision at this input slew
> rate that happens faster than the propagation delay to the output -- but
> this is just an inference because the internal nodes are not accessible for
> measurement.)  For this application, the small amount of internal
> hysteresis of the LT1719 and LT1720 is very beneficial.
>
> Best regards,
>
> Charles
>
>
>
>
>
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