[time-nuts] Using CPLD/FPGA or similar for frequency divider
Tom Van Baak
tvb at LeapSecond.com
Tue Jun 2 15:27:21 EDT 2015
> Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic?
> David Partridge
Yes, please consider it. I would be very interested in the results.
We measured under 2 ps jitter for the PIC dividers  used with the cute little TADD-2 board . One of these days I should measure your divider board with the same setup to see how it compares with a PIC. Like a CPLD/FPGA the PIC has the advantage of being fully synchronous and all on one die.
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