[time-nuts] Using CPLD/FPGA or similar for frequency divider

Bob Camp kb8tq at n1k.org
Wed Jun 3 11:10:42 UTC 2015


Hi

As always, the real answer it “that depends”. 

If your objective is wide band phase noise and you want to start from 100 MHz and get 10 MHz (fig 6 in
the Lamda paper), you can get at least another 6 db with a simple divide by 10 chip than with all the 
fancy stuff. 

Bob

> On Jun 3, 2015, at 12:17 AM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
> 
> You can always cleanup the outputs of the CPLD or FPGA by resynchronising the outputs to the input clock using a dedicated D flipflop for each output. 
> 
> Bruce
> 
> 
> 
>     On Wednesday, 3 June 2015 3:22 PM, Bob Camp <kb8tq at n1k.org> wrote:
> 
> 
> Hi
> 
> A lot depends on exactly which CPLD or which FPGA you are looking at and how 
> they put the guts of it together. If you find one that is “just right” it *might* be within
> 10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention
> and the AC that leaves a bit of room. 
> 
> If you have a part with a bias generator in it, just forget about using it. You will have all 
> sorts of strange spurs that come and go. They will be broadband. They will take the 
> noise floor up into the 100 dbc / Hz range in some cases. 
> 
> If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers
> like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. 
> 
> As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz
> you could expect under similar conditions with something like AC or faster CMOS. You 
> are more likely to get there on a fast CLPD than on an FPGA. Either way you can run
> into bum parts. 
> 
> Bob
> 
>> On Jun 2, 2015, at 9:13 AM, David C. Partridge <david.partridge at perdrix.co.uk> wrote:
>> 
>> Is this a sensible thing to consider doing?  Or would I be better sticking to AC/HC/AHC/LVC logic?
>> 
>> Regards,
>> David Partridge 
>> 
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