[time-nuts] GPS/SDR project design feedback needed

[John Seamons]

Hi group,

Please email any follow-up to me directly, and not to the list, unless it is relevant to the GPS aspect.

My little GPS / SDR add-on board project for the BeagleBone Black (GPS front-end + FPGA + ADC) is ready for first PCB fab. But I'd like to get some feedback on the design before I spend money. I'd particularly like to hear from any of you with EMI/EMC, FCC testing or PCB DFM experience.

While the software-defined GPS on the board is fun to play around with, and educational if you've ever been curious about the details of a functioning GPS receiver, this board will probably never be the basis of a GPSDO because of the unknown quality of the L1 VCO inside the front-end chip. You can supply a high-quality external 16.368 MHz clock to the VCO PLL, but I don't think that's good enough without knowing the PLL quality. But I don't understand the fine points of GPSDO design, so maybe someone can comment.

Live prototype SDR: <http://www.jks.com:8073> (password is 'kiwi')
Design review document: <www.jks.com/docs/wrx/wrx.design.review.pdf> (60 pages, which I don't expect anyone to fully read)
PCB Gerbers and sources: : <https://github.com/jks-prv/Beagle_SDR_GPS>
History: <www.jks.com/wrx/wrx.html>

Thanks in advance!
John