[time-nuts] Using CPLD/FPGA or similar for frequency divider

[Richard (Rick) Karlquist]

I used a CPLD in a 900 GHz (that's right 900 GHz) optical
sampling scope timebase.  It was great because you just
write a 17 bit counter in VHDL and there it is.  You
don't have to know anything about building digital
hardware any more (40 years of experience wasted).
Nobody cares about look ahead carry, etc.
I cleaned up the timing with conventional logic, so
I don't know what the jitter of the CPLD was.
We needed jitter in the low fs, so I am sure
the CPLD was not OK without cleaning up, but
then that was a lunatic fringe project.

Rick Karlquist N6RK

On 6/2/2015 6:13 AM, David C. Partridge wrote:
> Is this a sensible thing to consider doing?  Or would I be better sticking to AC/HC/AHC/LVC logic?
>
> Regards,
> David Partridge
>
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