[time-nuts] Using CPLD/FPGA or similar for frequency divider
Richard (Rick) Karlquist
richard at karlquist.com
Sat Jun 6 11:27:31 EDT 2015
The counter only had to run at ~50 MHz, on account of our
mode locked laser ran at that frequency. I don't remember
what the CPLD was rated at.
On 6/5/2015 8:19 PM, Hal Murray wrote:
> richard at karlquist.com said:
>> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
>> timebase. It was great because you just write a 17 bit counter in VHDL and
>> there it is. You don't have to know anything about building digital
>> hardware any more (40 years of experience wasted). Nobody cares about look
>> ahead carry, etc.
> Is that really true? Or perhaps, what fraction of the digital design space
> does it apply to?
> How fast was your counter running? How fast would it run? Was it a simple
> counter or was there enable/up/down/load type gating involved?
> What would you have done if you needed to run a bit faster? Could you buy a
> faster chip? How much more could you get with tricky logic?
> I agree that modern tools and parts have allowed a lot more people to build
> digital circuits.
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