[time-nuts] Using CPLD/FPGA or similar for frequency

Attila Kinali attila at kinali.ch
Mon Jun 15 18:14:01 EDT 2015


On Thu, 11 Jun 2015 14:22:58 +0000
Alan Ambrose <alan.ambrose at anagram.net> wrote:

> A clever interpolator for frequency or TIC would kill it -
> for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
> a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
> and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16
> bit ADC - and 1pS should be easy

Which architecture for the FPGA do you have in mind? The delay
line method (which is the most common one for FPGAs) has an intrinsic
limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude
conversion by charging a capacitor (both include a Nutt interpolator).

Using this technique, it might be possible to get into the 1ps ballpark,
if the design is done carefully (according to Richard McCorkle, the
limiting factor for the PICTIC II was the ADC of the PIC, followed by
the stability of the reference clock).

			Attila Kinali

-- 
I must not become metastable. 
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability. 
I will permit it to pass over me and through me. 
And when it has gone past I will turn the inner eye to see its path. 
Where the metastability has gone there will be nothing. Only I will remain.




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