[time-nuts] Divider circuit for Rubidium Standard

[Bob Camp]

Hi


> On May 19, 2015, at 7:10 PM, Richard (Rick) Karlquist <richard at karlquist.com> wrote:
> 
> 
> 
> On 5/8/2015 2:19 PM, Bob Camp wrote:
> 
>>> On May 7, 2015, at 11:09 AM, Attila Kinali <attila at kinali.ch> wrote:
>>> 
>>> On Wed, 06 May 2015 18:09:03 -0700
>>> "Richard (Rick) Karlquist" <richard at karlquist.com> wrote:
>>> 
>>>>> A standard input on a frequency counter is not a very demanding thing in the hierarchy of
>>>>> TimeNut signals. You can drive any of them with some pretty simple logic gate based
>>>>> circuits. No need to spend a lot of money.
>>>> 
>>>> Logic gate, yes.  Comparator, no.
>>> 
>>> This reminds me a lot of a similar discussion a couple of weeks ago.
>>> (where the issue boiled down to noise bandwidth)
>>> 
>>> What is the problem with a comparator vs a logic gate?
>>> What makes the logic gate supperior?
>>> 
>>> 			Attila Kinali
>>> 
> 
> The comparator as a squarer circuit is folklore that unsophisticated
> users want to believe in, because it is seemingly the easiest way
> to get the job done.  Wouldn't it be wonderful to be able to put in
> any signal from -30 dBm to +15 dBm and get a perfect square wave
> out with no effort?  Unfortunately, what a comparator looks like
> is a very high gain differential amplifier that is slew rate limited.
> The threshold voltage input must be extremely low noise or it
> will introduce jitter.  Even if the input pin is clean, there is
> internal noise.  Driving it will a low level signal will produce
> a jittery output for obvious reasons.  The trouble is that if you
> drive it with a high level signal, the jitter doesn't go away because
> the input stage is already in saturation.  Also, the effective noise
> figure of the comparator is usually high.  Making the comparator
> faster exacerbates the problem.  Read papers on "zero crossing detectors" such as John Dick's 1990 paper in PTTI and you will
> see that a comparator is the exact opposite architecture from
> the optimum one.  I hope that clears up the question.
> 
> Regarding logic gates:  it is not so much that there is something
> magic about gates; actually ECL gates are lousy.  It is just that
> comparators are so bad that almost anything else is better.

The only gates that seem to do very well are high speed (as in 74AC or faster) 
silicon CMOS. You need to run them with a fairly clean supply and feed them
with a p-p input that matches the supply voltage. Other than that, not a lot
of magic. Are they ideal - surely not. Will they hit 2x10^-13 ADEV at 1 second and 
drop from there as tau increases - yes they will.

Bob 

> 
> Rick Karlquist N6RK
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