[time-nuts] Divider circuit for Rubidium Standard

[Magnus Danielson]

Rick,

On 05/20/2015 01:10 AM, Richard (Rick) Karlquist wrote:
>
>
> On 5/8/2015 2:19 PM, Bob Camp wrote:
>
>>> On May 7, 2015, at 11:09 AM, Attila Kinali <attila at kinali.ch> wrote:
>>>
>>> On Wed, 06 May 2015 18:09:03 -0700
>>> "Richard (Rick) Karlquist" <richard at karlquist.com> wrote:
>>>
>>>>> A standard input on a frequency counter is not a very demanding
>>>>> thing in the hierarchy of
>>>>> TimeNut signals. You can drive any of them with some pretty simple
>>>>> logic gate based
>>>>> circuits. No need to spend a lot of money.
>>>>
>>>> Logic gate, yes.  Comparator, no.
>>>
>>> This reminds me a lot of a similar discussion a couple of weeks ago.
>>> (where the issue boiled down to noise bandwidth)
>>>
>>> What is the problem with a comparator vs a logic gate?
>>> What makes the logic gate supperior?
>>>
>>>             Attila Kinali
>>>
>
> The comparator as a squarer circuit is folklore that unsophisticated
> users want to believe in, because it is seemingly the easiest way
> to get the job done.  Wouldn't it be wonderful to be able to put in
> any signal from -30 dBm to +15 dBm and get a perfect square wave
> out with no effort?  Unfortunately, what a comparator looks like
> is a very high gain differential amplifier that is slew rate limited.
> The threshold voltage input must be extremely low noise or it
> will introduce jitter.  Even if the input pin is clean, there is
> internal noise.  Driving it will a low level signal will produce
> a jittery output for obvious reasons.  The trouble is that if you
> drive it with a high level signal, the jitter doesn't go away because
> the input stage is already in saturation.  Also, the effective noise
> figure of the comparator is usually high.  Making the comparator
> faster exacerbates the problem.  Read papers on "zero crossing
> detectors" such as John Dick's 1990 paper in PTTI and you will
> see that a comparator is the exact opposite architecture from
> the optimum one.  I hope that clears up the question.

The older HP counter manuals explained it very nicely too, as they 
illustrated the slew-rate & amplitude noise to time-noise conversion.

What do amazes me is the fact that I've yet to see a counter input 
channel which takes care to square up the signal properly, they rather 
provide the comparator after the obvious damping and AC-blocking 
conditioning. I can't even recall that there where much such shaping as 
a side-product.

> Regarding logic gates:  it is not so much that there is something
> magic about gates; actually ECL gates are lousy.  It is just that
> comparators are so bad that almost anything else is better.

Now, remind me why ECL is lousy, I can't recall there being very high 
gain in them, but fairly high bandwidth and they stay in the linear 
operation region.

PS. Sniffed the heat from a 1979 ECL based PM6674 counter as I was doing 
some checkout before put it in the hands of a friend.

Cheers,
Magnus