[time-nuts] Divider circuit for Rubidium Standard

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri May 22 19:15:20 UTC 2015


On Friday, May 22, 2015 10:48:16 AM Gerhard Hoffmann wrote:
> Am 21.05.2015 um 23:32 schrieb Magnus Danielson:
> > On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:
> >> The counter front ends seem to be modeled after scope front ends
> >> and scope triggering circuits, where you can adjust the triggering
> >> level.  Any jitter in the triggering would normally only affect
> >> the interpolator.  The interpolators in general were no great shakes,
> >> so the triggering wasn't the limiting factor.
> > 
> > Depends on the signal.
> > 
> >>> Now, remind me why ECL is lousy, I can't recall there being very high
> >>> gain in them, but fairly high bandwidth and they stay in the linear
> >>> operation region.
> >>> 
> >>> 
> >>> Magnus
> >>> _______________________________________________
> >> 
> >> ECL is bad because the voltage swing is low; because as you say,
> >> a lot of the circuitry is in the active region all the time, and
> >> because the current source in the emitters generates a lot of
> >> noise.
> > 
> > Yes, it is bound to have 1/f noise with it's 50 Ohm current load.
> > I was thinking about the continuous current, as I do know of the
> > gating effect. Today there is other interface standards having lower
> > swings than ECL.
> > 
> >> In the early 1990's, I thought I had proved that the high ECL
> >> noise was mostly common mode and that you could reduce it
> >> 20 dB by using a transformer to couple the output.  Alternately,
> >> a good differential amplifier with high CMRR would do the trick.
> >> I had actual measurements to back up this theory.
> >> 
> >> Subsequently, other people tried to reproduce this and could not.
> >> By that time, I had moved on and didn't have the bandwidth to
> >> continue to own the problem.
> >> 
> >> It would make a nice project for some time-nut to prove or disprove
> >> my hypothesis regarding ECL.
> >> 
> >> ECL line receivers as squarers are not as bad as comparators, but
> >> are much noisier than 74AC.
> > 
> > Interesting.
> > 
> > Don't have a lot of ECL lying around, but some toys that might 
measure
> > things.
> 
> Could we agree on a test procedure?
> 
> A friend of mine did some tests for synthesizers in mil. avionics and he
> told me
> that Motorola's MOSAIC3 process was the worst thing that has hit the
> planet wrt
> phase noise. That was used for a lot of fast ECL. (Some years have
> passed since
> he made the test.)
> 
> Comparators have their advantages, too. At least, someone has been 
thinking
> about dispersion, constant flowthrough time against frequency and
> overdrive;
> there are even specs that include overdrive. Just that comparators can
> switch
> cleanly at mV levels does not mean that they are to be used that way.
> 
> More gain may mean more noise voltage, but it also means less time 
spent
> in the transition region. Once the decision has been made the noise is
> squelched
> anyway.  And I prefer setting the bandwidth with thin film Rs and np0
> capacitors,
> not with oversized junctions.
> 
> The fairest shootout between the logic families that we have is the 
LTC6957.
> 
> < http://cds.linear.com/docs/en/datasheet/6957f.pdf >
> 
> Probably just bondout options of the same chip. The PECL version wins
> hands-down, LVDS is worst and CMOS is in-between.
> 
> Especially at low offsets PECL is best, that clearly contradicts the
> above-assumed 1/f problem and the lower swing standard of today
> comes out worst.
>
> regards, Gerhard
> 
> 
> 
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The LT6957 dtasheet PN curves differ from what I measured with a 10-MHz 
input in that when shielded from air currents the flicker noise corner is 
much lower than 100Hz offr a 100MHz input.
I have only tested the LTC6957-4 evaluation board.

Bruce




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