[time-nuts] Digital Phase Lock Loops

[Charles Steinmetz]

Martyn wrote:

>I want to design a digital phase lock loop.
>I intend to lock a 10 MHz ultra low noise oscillator that we make to 
>an external frequency standard.
>I need a digital PLL as I'm trying to get a loop bandwidth < 0.1 Hz.
>Has anyone had any experience of Digital PLL's or can point me to 
>any documents published?

Jim wrote:

>I would think that any of the GPS disciplined oscillator schemes 
>that have been discussed on the list would be a good start.

Alexander and Dave recommended Roland Best's PLL treatise.

Re: projects discussed on-list -- These are almost all FLLs, not 
PLLs, and almost all have significant design shortcomings at the 
stage of development we have seen.

Re: Best's treatise -- No one book is anywhere near a sufficient 
resource.  Best's is certainly one of the must-have books, but so are 
Gardner's (the single best, IMO), Egan's, Stephens's, Wolaver's, and 
a half-dozen others.

As to designing digital PLLs, I'm not aware of any "cookbook-style" 
approaches.  One reason is that there are so very many ways to build 
"digital" PLLs.  (Note that analog PLLs using logic gates for the 
phase or phase-frequency detector are often called "digital" PLLs, 
but they are not.  Some people call what you are probably thinking of 
"all-digital PLLs" ("ADPLLs"), to mark this distinction, but in 
reality many bona-fide DPLLs are not really *all* digital.  In 
particular, practical DPLLs often use analog phase or phase-frequency 
detectors before digitizing (but some really are all digital, 
including the PD/PFD).

A good exemplar of DPLLs using analog PD/PFDs are the Quartzlock PLLs 
that Ole Petter Ronningen mentioned in his post of 17 Oct.  The 
architecture described in the Quartzlock documents is essentially the 
same as what I have used with good success.  I and Q signals are 
developed from the controlled oscillator and fed to I and Q phase 
detectors, where they are compared with the reference 
oscillator.  The PD outputs are digitized and the loop filter and 
tuning signal are implemented in software.  Note that you want lots 
of bits in the tuning DAC -- more than you might think you 
need.  Quartzlock uses two, 16-bit DACs deployed to give 24 bits of 
fine control with another 8 bits of coarse control to trim long-term drift.

I develop the quadrature signals in the analog domain before 
squaring, or with a quadrature divide-by-4 after squaring, depending 
on which has lower PN at the frequency of interest.  The Quartzlock 
modules are designed to work over a wide range of frequencies, so 
they generate the "Q" signal with a programmable delay line to a 
granularity of 0.5nS.

In my experience, this basic architecture works extremely well and 
can readily produce bandwidths of 1mHz or lower.  However, the devil 
is in the details and there are a *lot* of details that need to be 
worked out before you have a useful DPLL.

Best regards,

Charles