[time-nuts] algorithms and hardware for comparing clock pulses

[Bob Camp]

Hi

Simple approach:

Use a pair of tri-state buffers. 

Both have their outputs hooked to the cap through resistors.

One (call it A) has its signal input grounded. The other (call it B) has
its signal input tied high. Both of the tri-state controls normal sit in the 
“off” (= output is tri-state) condition. 

When I turn A on, the cap discharges. If instead, I turn B on, the cap 
charges. If neither is on, the cap changes voltage only due to leakage
current. 

Let’s say I have a long R/C on A and simply use it to discharge the cap 
to zero. It’s there only to set a starting value on the cap. The R/C could be
just about anything. 

Let’s also say that I feed a variable width pulse into B. While the pulse has
the gate control “on” the cap charges. The voltage on the cap is proportional to
the well known R/C time constant formula and the width of the pulse. 

Once the pulse is gone, I fire up the A/D and read the voltage. After I have
the voltage I put the cap back to ground with A. 

====

So what can go wrong?

1) I have the cap in the “both gates off” state to long and all I’m 
reading is the impact of leakage current.

2) My pulse is to wide and the R/C maxes out.

3) My pulse is long enough that my resolution goes below my desired
resolution target. 

4) The resistance is low enough that the gate output R gets into the 
act.

5) The C is so small that trace stray C (and input C’s) get into the act. 

6) The current into the R is so high that the gate current limits at the 
start of the charge cycle. 

7) The caps or resistors are not stable so the system is not repeatable. 

8) Your ADC has some pathogenic thing it does when it converts that shorts
the cap to ground. ( = you have a really weird ADC). 

Except for leakage current, everything is controllable in the design. Some
of the stuff above can be modeled (or measured) to minimize it’s impact. There
are more subtle issues like the fact that the gate has a different propagation delay
low to high than high to low. That will stretch the pulse a bit. If you get really fast
on the pulse, the output of the gate gets into the act a couple of ways. 

Bob


> On Sep 24, 2015, at 2:31 AM, Bill Hawkins <bill at iaxs.net> wrote:
> 
> Perhaps I can do this in words, as I have no schematic software.
> 
> Start with the input to your favorite microprocessor's A/D converter.
> Connect it to a suitable (more later) capacitor to analog ground.
> Connect a cmos switch across the cap and call it S2. When S2 is on, it
> discharges the cap.
> 
> Now build or buy a constant current generator connected from a suitable
> positive voltage to another cmos switch called S1.
> When S1 is on, all of the current generated flows to analog ground.
> 
> To make it all work, connect the anode of a diode from the junction of
> the current source and S1 to the cap and analog input.
> 
> When S1 is on, no current gets to the cap. When S1 is off, all of the
> current gets to the cap, if S2 is off. This causes a linear buildup of
> voltage across the cap, for a suitable time.
> 
> When 1 PPS pulses are compared, suitable means one second to charge to
> almost the maximum that the micro A/D supports.
> The value of I is chosen to overwhelm diode leakage and A/D input
> current. The value of C follows.
> 
> All that remains for a working system is a pair of flip-flops to control
> S1 and S2.
> FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
> FF1 is on, S1 is off.
> FF 2 is set by PPS 1 and cleared by an output from the micro when the
> A/D conversion is done. When FF2 is on, S2 is off.
> 
> And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
> conversion occurs, and be reset to zero volts when the micro is done
> processing the input.
> 
> This gives the micro a linear conversion of pulse difference time rather
> than an RC exponential value.
> 
> Feedback controllers do better with linear error signals.
> 
> But all of this is wasted if the PPS signals are not accurate due to
> things that affect pulse rise and fall times.
> 
> If the above was not adequately clear, please ask for clarification. Or
> do a schematic and ask for corrections.
> 
> Bill Hawkins
> 
> P.S. This will not work well for small differences between PPS 1 and 2.
> It will work if the goal is 50% difference, or 90 degrees phase shift.
> 
> 
> -----Original Message-----
> From: Can Altineller
> Sent: Wednesday, September 23, 2015 2:56 AM
> 
> --------%< ------
> 
> 4. I think an analog solution like Bill Hawkins described, would be best
> suited for this task. But I have not understood it enough to build it.
> 
> Best Regards,
> C.A.
> 
> 
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