[time-nuts] Looking for ECL divide by 3 with symmetry

[Hal Murray]

eb at telight.com said:
> I need to build an ECL divide by 3 circuit to run at about 50 MHz input.  I
> know there are lots of examples out there, but I vaguely recall years  ago I
> stumbled upon one or more that also provided more of a symmetrical  output
> nearly 50 percent duty factor, by using both input edges, or  reclocking
> with another FF.

If you you have a square wave input, you can build a clock doubler with an 
XOR and FF.  That gives short pulses, but they are wide enough to clock FFs 
using that technology.  You can add a delay line to make the pulse wider.  
(PCB traces are 6 inches per ns so you can get short delays that way.)


If you are working with ECL, many parts use differential clocking so you can 
cleanly clock on the other edge by swapping pins.  So you could make a 50-50 
divide by 3 from 3 FFs: 2 for a count-to-3 FSM, and 1 clocked on the other 
edge, and a small cloud of gates.

The FSM has 3 states.  FF 1 is on for cycle 1.  FF 2 is on for cycle 2.  Both are off for cycle 3.

FF 3 is FF 1 delayed by a 1/2 cycle.  The output is FF 1 ORed with FF 3.

I think the input to FF 1 is not (FF 1 or FF 2)
The input to FF 2 is FF 1.
The input to FF 3 is FF 1.


-- 
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