[time-nuts] 1 PPS 50-ohm driver

[Bob Camp]

Hi

If the PPS is being generated by an FPGA or a MCU, inverted is as easy to generate as
not inverted. Many decades ago an “un buffered” inverter was the speed king. These days,
as you have noticed, the difference between inverters and bufferers is not significant. For
non-inverting setups the ‘125 and ‘126 gates are normally used.

Bob

> On Apr 17, 2016, at 10:59 AM, Wojciech Owczarek <wojciech at owczarek.co.uk> wrote:
> 
> A slightly naive question(s) perhaps, so do excuse me, but I reckon this is
> a good opportunity to ask since I am approaching the same design questions
> (this is a 1PPS in + 1PPS out driver for the Beaglebone Black, to/from its
> PTP clock). This involves 5v / 3.3v conversion but that's another topic.
> 
> IC spec sheets are one thing, but since the Time Nuts have seen and done it
> all... Why an inverting buffer? Is there an advantage in using inverted
> logic for 1PPS? I have come across other timing kit that internally uses
> falling edge, which is eventually inverted when interfacing with the
> outside world. Is this common, and why? If my output is rising edge right
> from the PWM pin I'm using to generate my 1PPS (again, separate topic), do
> I gain anything by inverting it and using an inverting buffer? Is this a
> matter of different rise/fall propagation delays over the various ICs?
> 
> Thanks,
> Wojciech
> 
> -- 
> -
> 
> Wojciech Owczarek
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