[time-nuts] DMTD - analog multiplier vs. diode mixer ?

[Bob Camp]

Hi


You can use a D flip flop to sample (down convert) a signal. You may or 
may not get into metastability problems when you do.

If you treat the gate inputs as -1 and +1 rather than 0 and 1, the XOR is a 
multiplier. If you put two signals into the gate and look at the output on a 
spectrum analyzer, you get the expected multiplier output. The *why* of
the -1 and +1 stuff is something I will leave to others. It’s a bit involved.

The 74LVC is a good series to use. The NC7SZ series is also a good one. 
In both cases, you will get a better noise floor at 5.5 V than at 3 V.

Bob

> On Jan 8, 2016, at 9:19 PM, Li Ang <lllaaa at gmail.com> wrote:
> 
> Hi Bob,
>    In some article, I see people use a D-flipflop to sample the input
> signal with reference clock. When you want implement a mixer what's the
> difference between D-flipflop and XOR gate? Acorrding to my understanding,
> to multiply 1bit with another, I should use an AND gate, right?
>    When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?
> 
> Thanks
> 
> BI7LNQ
> 
> 
> 2016-01-09 6:42 GMT+08:00 Bob Camp <kb8tq at n1k.org>:
> 
>> Hi
>> 
>> The board I have uses high speed CMOS single gate XOR’s. They have a
>> pretty good
>> phase noise floor (-170’s) so they should be pretty reasonable.
>> 
>> Bob
>> 
>>> On Jan 8, 2016, at 12:16 PM, Richard (Rick) Karlquist <
>> richard at karlquist.com> wrote:
>>> 
>>> 
>>> 
>>> On 1/7/2016 3:11 PM, Bob Camp wrote:
>>>> Hi
>>>> 
>>>> If your intention is to run a mixer with saturated inputs …. just run
>>>> an X-OR gate. It will handle the high level signals much better than
>>>> an over-driven analog part.
>>> 
>>>> Bob
>>>> 
>>> 
>>> If you look at the schematic of an XOR gate IC and compare it
>>> to the schematic of, for example, an MC1496 mixer, you will
>>> see a lot of similarity.  If the gate is of the ECL type,
>>> it will have the addition of emitter followers, but that
>>> it a minor detail of implementation.  I'm not sure there
>>> is a huge difference.  ECL is a great logic family in
>>> general (self-confessed ECL-phile here :-) but it is
>>> probably the worst for phase noise, compared to the
>>> saturating logic types.
>>> 
>>> Rick Karlquist N6RK
>>> _______________________________________________
>>> time-nuts mailing list -- time-nuts at febo.com
>>> To unsubscribe, go to
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>> and follow the instructions there.
>> 
>> _______________________________________________
>> time-nuts mailing list -- time-nuts at febo.com
>> To unsubscribe, go to
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
>> 
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.