[time-nuts] DMTD - analog multiplier vs. diode mixer ?

Alexander Pummer alexpcs at ieee.org
Sun Jan 10 16:08:07 EST 2016


"generate stable high -frequency signals  with d flip-flops as digital 
mixers ans all -IC low frequency phase -locked loop", by R.Treadway and 
L.J. Reed, page 78 Electronic design 1 January 1972
Resistot array denounces D flip-flop  mixer page 184 EDN 12 April 1990
digital frequency subtract or  EDN 1 April 1981
Kamil Kraus: Die Arbeitsweise eines einfachen Digitalmischer, Seite 72 
Elektronik Heft 24, 1980 a very good explanation of the function of the 
digital mixer-- in German
Design ideas; D flip-flop sutracs frequencies by Richard Kochis, 
Hewlett-PackardCo Ft. Collins ,CO, Gerald Flachs , New Mexico State 
University, Las Cruces, END 15 April, 10981 page 149
Robert a Pease National Semiconductor Corp : Four ICs subtract 
frequencies, EDN 1 April 1981
"Digitalis keverofokozat tervezese",  Zombay Frerenc, Radiotechnika, 
Seite 244 # 5 1996,  a complete design of the digital mixer with 
detailed theory and example in three consecutive issue of the magazine 
Radiotechnika -- in Hungarian.
By using that literature I designed many frequency synthesizers 
containing D flip-flops as a digital mixer

73
KJ6 UHN
Alex
[alias Dr.Dipl.Ing. Alexander Pummer, PCS Consultants]
US patents:  many if you are interested I will send you a list


On 1/10/2016 10:56 AM, Attila Kinali wrote:
> On Sun, 10 Jan 2016 14:30:41 +0100
> Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
>
>>> SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
>> A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
>> Also, as I mentioned the PFD directly after, you could have concluded
>> that was not what I intended.
>>
>> A SR-flip-flop with no illegal input states is easy to build from a 74HC00.
> The illegal input states were my concern, indeed. And a quick google
> didn't show up anything to disperse these....not until I started reading
> the 4046 datasheet in detail.
>
> But there is one thing about the arangement of the SR FF in the 4046[1]
> that bothers me:
> Although S = R = 1 is valid, it does lead to the output oscillating
> between 0 and 1.
>
>
> 			Attila Kinali
>
>
> [1] Ti CD74HC4046A Datasheet
> http://www.ti.com/lit/ds/symlink/cd54hc4046a.pdf
>




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