[time-nuts] Generating a solid PPS from 10Mhz source

Gerhard Hoffmann dk4xp at arcor.de
Thu Jan 14 12:29:15 EST 2016


Am 14.01.2016 um 15:50 schrieb Vlad:
>
>
> I was thinking to make a frequency divider by using FPGA. Here is my 
> attempt to implement it using VHDL.
> This is frequency divder plus D flip-flop which I was planed to use as 
> source of 60Hz for my Telechron clock.
> However I never implement it in HW. Instead I was using STM32F4 with 
> its timers.
> The purpose was to divide 9.8304 Mhz OCXO output by 81920 to get 60Hz 
> and use the D flip-flop to keep output in sync.
> Some day I'll return to this with my soldering iron in hands. ;-)
>

A year or 2  ago, I have posted a VHDL solution here that fits into half 
a Xilinx
Coolrunner 2C64A-5. When the input clock is pretty (50% duty cycle) it 
runs at
200 MHz in. (tested)
The 2C64 does not take a lot of space:

< 
https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink 
 >

The bottom row of test circuits are a 100->200 MHz doubler and a 
200->400MHz doubler
with a wide SAW filter to kill the harmonics.

Since the 10811 oven is so big, the Coolrunner will find a niche on the
universal VCXO carrier board I talked about 6 Weeks ago. Also, Charles
Steinmetz' version of the Wenzel and the LT limiter, so we can compare
them easily.

I have chosen to use W.J. Riley's ring mixer PLL and not the AD9901, no 
point to
re-invent the wheel. But that will cost the ability to lock on external 
1pps; only
lock to external 10 MHz is provided.

BTW. I have coded an AD9901 work-alike in VHDL that could also fit into 
this
Coolrunner, but it was never tested because we have solved our problem 
otherwise.

regards, Gerhard





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