[time-nuts] Generating a solid PPS from 10Mhz source
kb8tq at n1k.org
Tue Jan 19 17:58:24 EST 2016
If you fire up the FPGA and measure it, you will find a sub picosecond jitter on a signal passing through it.
If you use the internal PLL or DLL in an FPGA, you might indeed see close to 1x10^-12 ADEV in some cases.
In general you should be able to get into the parts in the 10^-13 range even with an internal FPGA PLL.
Delay wise, you have the advantage on the FPGA that the “internal” gates are running 100’s of ps delay wise
rather than a couple of ns delay. You still have i/o delay and routing delay to deal with. As mentioned in another
post, delay is very much not the same thing as jitter.
> On Jan 19, 2016, at 3:37 PM, Vlad <time at patoka.org> wrote:
>> The nice thing about a FPGA (or CPLD) is that they come with a cute
>> timing analyzer. You can indeed
>> answer questions like this with a quite high level of confidence. That
>> *assumes* that you bother to set
>> up the timing analyzer :)
> That true. Its nice looking "Timeng report". I saw the numbers there.
> Performance Summary for Xilinx XC32C32A:
> Min. Clock Period 3.300 ns.
> Max. Clock Frequency (fSYSTEM) 303.030 MHz.
> Clock to Setup (tCYC) 3.300 ns.
> Clock Pad to Output Pad Delay (tCO) 3.700 ns.
> Its always few nanoseconds delays. Which quite sad, since I was expect better from CPLD. With this "background", PICDIV looks much more attractive with its 2ps Jitter.
> Long live for Tom and Microchip engineers !
> D flip-flop looks like a good solution. However, now I am thinking it could do its own "timing correction" (skew/delay) to the signal. Looks like "classic" 74LS74 has similar delays as CPLD has.
> Nothing is perfect. ;-)
>> Regardless of the divider it’s self, you will have the sine to
>> square conversion. You also
>> may have a sensitivity on a square back to sine conversion. All of it
>> (and the divider) will have both temperature
>> and voltage sensitivity. Most of that will be in the “measure it and
>> see” category.
> I was using Wenzel "two 3906" solution. BTW, when I compare it to "74AC", I saw more spikes with it:
> Which make me thinking that 74AC/74HC logic make the conversion more "smooth". However, in my observations, I saw that "two 3906" is close to reflect the actual signal coming from OCXO. I mean if OCXO has some spike (noise), than it immediately will be noticed by "two 3906" schema. 74AC/74HC solution somehow remove/ignore it. I don't know how to explain this. Its just from my setup and my observation and probably not correct at all.
>> Based on measurements, all of it comes out in the “no big deal”
>> range for normal applications.
>>> On Jan 18, 2016, at 12:28 PM, Vlad <time at patoka.org> wrote:
>>> Looking to the complex solutions for the frequency divider (CPLD/MCU), I start to think about skews and propagation delays. Its not obvious from the first glance. But I think such things exists.
>>> It could be interesting to compare the numbers. Is it worth to consider some correction to avoid phase difference between of input and output ?
>>> On 2016-01-18 08:59, cfo wrote:
>>>> On Wed, 13 Jan 2016 09:22:09 +0000, Jerome Blaha wrote:
>>>>> Is there an easy circuit to build that can consistently deliver a 1 PPS
>>>>> from a 10MHz source with excellent resolution and repeatability?
>>>> Ulrich B. has made an AVR 1PPS, for those that uses AVR's instead of PIC's
>>>> AVR PPSDIV 2008-09-06 - in bottom of page.
>>>> The Mega8 version should be easy to port to an Arduino clone
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