[time-nuts] Generating a solid PPS from 10Mhz source
attila at kinali.ch
Wed Jan 20 06:28:24 EST 2016
On Mon, 18 Jan 2016 14:34:56 -0500
Bob Camp <kb8tq at n1k.org> wrote:
> The nice thing about a FPGA (or CPLD) is that they come with a cute timing analyzer. You can indeed
> answer questions like this with a quite high level of confidence. That *assumes* that you bother to set
> up the timing analyzer :)
I wouldn't trust that timing analyzer too much. We just build a TDC using
an Cyclone 4 FPGA here (actually, porting the OHWR delay line TDC from
Spartan to Cyclone) and the timing analysis was... weird, at best.
Although the average delay was about right (40ps and 120ps) it only
showed a two element structure, ie the delays of the chain were
"40ps, 120ps, 40ps, 120ps,..." without any higher level structure
(which should have shown). The test results showed a quite more
detailed structure with few delays over 100ps and most being between
20ps and 80ps. Interestingly, some were close to 0ps, for which
we have no explanation good explanation.
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