[time-nuts] Generating a solid PPS from 10Mhz source
kb8tq at n1k.org
Wed Jan 20 17:56:31 EST 2016
> On Jan 20, 2016, at 6:28 AM, Attila Kinali <attila at kinali.ch> wrote:
> On Mon, 18 Jan 2016 14:34:56 -0500
> Bob Camp <kb8tq at n1k.org> wrote:
>> The nice thing about a FPGA (or CPLD) is that they come with a cute timing analyzer. You can indeed
>> answer questions like this with a quite high level of confidence. That *assumes* that you bother to set
>> up the timing analyzer :)
> I wouldn't trust that timing analyzer too much. We just build a TDC using
> an Cyclone 4 FPGA here (actually, porting the OHWR delay line TDC from
> Spartan to Cyclone) and the timing analysis was... weird, at best.
Been there / done that on both parts. The timing analyzer is doing what it is supposed to do =
analyze the worst case delays against the constraints you provided. It then makes sure that
the data gets where it needs to go “in time” for it to be correct. The approach is typical semiconductor
industry “six sigma over a billion cycles on a billion devices each with a billion gates” sort of thing.
The result is a part that does indeed work. It’s not much use for predicting things like jitter.
> Although the average delay was about right (40ps and 120ps) it only
> showed a two element structure, ie the delays of the chain were
> "40ps, 120ps, 40ps, 120ps,..." without any higher level structure
> (which should have shown). The test results showed a quite more
> detailed structure with few delays over 100ps and most being between
> 20ps and 80ps.
Some of which are fabric (routing) delays). Some of which are simply the analog nature of digital
circuits (noise matters, gain matters). Some of them may be a result of auto routing the design rather
than manually placing everything. (Yes manual routing can help. It’s a major pain for fairly little gain).
> Interestingly, some were close to 0ps, for which
> we have no explanation good explanation.
The explanation is fairly simple, you have a clock and a “data pulse” flying down the delay / carry chain. With
an ASIC you could make sure they take a very linear route through the silicon. With a FPGA you can’t do that.
Both are routed through this and that. When you get down to the ps level, there is no guarantee which one
gets there first. Even if there was, the aperture time on the flip flops is sensitive to things like voltage and temperature.
What you see this time may not be what you see that time. There are a whole bunch of papers on all of this.
Bottom line, not all indicated data patterns can be placed in a nice orderly plot ( = you don’t know which one
came first). About the only way to order them is to count the zeros. Not perfect, but about the best you can do.
> Attila Kinali
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