[time-nuts] Generating a solid PPS from 10Mhz source
attila at kinali.ch
Thu Jan 21 05:48:08 EST 2016
On Wed, 20 Jan 2016 17:56:31 -0500
Bob Camp <kb8tq at n1k.org> wrote:
> > Interestingly, some were close to 0ps, for which
> > we have no good explanation.
> The explanation is fairly simple, you have a clock and a “data pulse”
> flying down the delay / carry chain. With an ASIC you could make sure they
> take a very linear route through the silicon. With a FPGA you can’t do that.
> Both are routed through this and that.
We placed the delay line manualy and run the calibration loop of the
OHWR TDC. Which does a histogram over all bins excited with a (hopefully)
uncorrelated ring oscillator. We tried both the OHWR temperature to binary
encoder and a "count all zeros/ones" version. Both showed the same behaviour,
ie that some bins hardly see any hits. Yes, i would expect this kind of
thing in general, due to the layout/routing of the wires in the FPGA. But
I would expect it to have some kind of regularity, a kind of pattern in the
distance between these un-excitable bins. But there is none. That's why I'm
saying we have no good explanation for it.
We have not had the time to analyze the routing in detail to see whether
there is anything fishy there. I will try to squeeze that in, if possible.
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the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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