[time-nuts] High rate, high precision/accuracy time interval counter methods

[Bruce Griffiths]

Since the GSPS sampling ADCs all appear to use an input buffer with relatively low value resistors between the differential inputs or connected to a midpoint bias voltage, some kind of high impedance buffer is needed between the TAC capacitor and the ADC input when using such ADCs. The highest clock frequency for capacitive input pipeline ADCs appears to be about 300MHz. A 1GSPS ADC relaxes the performance requirements of the TAC significantly making it easier to achieve 1ps or less noise.The trade off is that a discrete TAC may not be fast enough due to parasitic bond wire inductances etc. All monolithic TACs with 1ps resolution have been designed using standard IC processing.
Bruce
 

    On Tuesday, 10 May 2016 12:14 AM, David <davidwhess at gmail.com> wrote:
 

 Sure, and then we are back to a transition midpoint timing TDC.  Or AC
couple it for a centroid timing TDC.  These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.

I was just wondering about the speed limitations of a time to
amplitude based TDC.  I am more comfortable with analog design than
using FPGAs.

On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:

>Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
>http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
>May be effective in that it has near Gaussian response with relatively low out of band SWR.
>
>Bruce 
>
>On Monday, 9 May 2016 3:01 PM, David <davidwhess at gmail.com> wrote:
> 
>
> How much will dielectric absorption in the capacitor affect the
>accuracy of the result with such a high conversion rate?  I am used to
>dealing with it on much longer time scales and higher resolutions.
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