[time-nuts] Commercial software defined radio for clock metrology

[Attila Kinali]

On Wed, 25 May 2016 16:01:51 +0000
"Sherman, Jeffrey A. (Fed)" <jeff.sherman at nist.gov> wrote:

> We found that in the studied units the limiting non-stationary noise
> source was likely the aperture jitter of the ADC (the instability of the
> delay between an idealized sample trigger and actuation of the sample/hold
> circuitry). However, the ADC's aperture jitter appears highly common-mode in
> chips with a second "simultaneously-sampled" input channel, allowing for an
> order-of-magnitue improvement after channel-to-channel subtraction. For
> example, at 5 MHz, the SDR showed a time deviation floor of ~20 fs after
> just 10 ms of averaging; the aperture jitter specification was 150 fs. We
> also describe tests with maser signals lasting several days.

I tried to understand where the aperture jitter comes from and why
it has such a huge common-mode. I asked a professor from Stanford
doing research on ADCs a couple of questions in this regard,
especialy whether he had any good references to read.

Apparently, most of the noise in ADCs is internally generated.
The two biggest contributors to aperture jitter seem to be thermal
noise in the clock path and power supply noise. Interestingly, power
supply noise comes mostly from the ADC itself and not from the external
power source. I've been told the voltage drop on the power grid due to
current spiking on chip can reach several tens of mV.

Beside that, most research on jitter induced ADC noise only considers
the clock jitter as source. There are very few that consider supply
induced jitter as well, but no numbers are given. A few also mention
substrate coupled noise, but according to the professor that is
negligible in reality. 

The professor was surprised at how much of the aperture jitter is
common-mode. He asked whether there was any explanation given by
Jeffrey or Roberts in the paper, which I had to deny. His best
guess was that the common-mode came either from external supply
or internal supply issues common to both channels. He also remarked
that the phase noise spectrum could give hints.

I personally do not think that the phase noise spectrum reviles anything.
There is just too much going on to say anything.

I think it would be interesting to try a board designed for low noise
operation and see what that would show (partially working on that already
for other reasons). I also found out that the sample-and-hold circuits
have a input voltage dependent delay component. So there is potentially
a phase shift dependent change in the noise floor.


				Attila Kinali
-- 
Reading can seriously damage your ignorance.
		-- unknown