[time-nuts] 1PPS to 32.768 khz

[Lee - N2LEE]

I have this (very smart) semi-retired design engineer friend named Craig who I first queried about this clock issue.
We always enjoy getting together in his lab or sitting outside enjoying the weather and good cigars. 

As usual I bug him with my crazy ideas as a way to educate myself or challenge him on how to solve a problem.
After I received some great suggestions from the Time-Nutz I sent a few of them to him for a second opinion.

Mark Sims suggestion (below) peaked Craig’s interest and got the juices flowing and into the junk box he went. :)

I thought you guys would enjoy hearing what he came up with and seeing a short video he sent me.

Lee


——
Lee,

I dug into my used junk box parts :-) and here is what I came up.

I used two 4060s, used the intermediate taps, in series to count 32,768 cycles greater than a 35kHz arbitrary oscillator. The final board will use a 555 but for now I used a Tek 500 series generator and 4060 tap wiring to allow power of two options plus/minus for testing.  The 4060 pair 2^15 or 2^16 (half cycle) output goes to a edge triggered D flip flop (74HC74 type) that resets the 4060s to stop the count and the 4060 Osc feed through output, pin 10, to the wall clock resonator input.  A Trimble Thunderbolt 1pps 50 Ohm loaded output is then used to clear the flip flop which releases the reset on the 4060s and the 32,768 count starts over.  Verified the counts with the Tek counter in "totalize" mode.  Is fun to see the output count active vs idle duty cycle vary with the nnn kHz Osc input Freq change :-)  I will have to attenuate the 5V output to an appropriate level for your clock but it looks like this will work for your clock project.

Let me know when you can bring the “jumbo clock” by so we can test it.

Here is a video showing you the 32.768 burst.

https://youtu.be/yNciXTv8Y7c

Craig
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Here's another way to do it for a wall clock display...   set up an oscillator/divider (or even a 555 timer) to generate a frequency close to, but faster than 65536 Hz.    Setup a 16 bit counter clocked by that signal. When the 1PPS signal arrives, start the counter.  After 65536 pulses the counter will overflow... stop the counter (and set up for the next 1PPS trigger) when that happens.   The Q0 output (lowest bit) from the counter will be a burst of 32768 pulses that repeats once a second.  Use that to drive your clock.   The slight pause between bursts of 32768 pulses will not be noticed on the clock display.

Mark