[time-nuts] uC ADC resolution (was: Poor man's oven)

Sat Jun 10 20:26:08 UTC 2017

Hi,

As a side comment. I've seen an OCXO misbehave such that it was 
bang-bang regulating. For a short while it was heating up and then the 
crystal was cooling down slowly until the heater was turned on again, 
shortly. The effect being that the temperature of the crystal was 
essentially a saw-tooth shaped thing, and the frequency and phase 
reflected that very clearly, and ADEV is full of the systematic noise of 
the oven.

For another OCXO I noticed a distinct bump in the ADEV at 7 s. I looked 
carefully and could even see the oscillation in the phase-data. Then I 
also found it in the oven current. Turned out that as I turned the oven 
on, it GREATLY overshot and rang as a bell on the overn 
current/temperature. The vendor was given notice and they dug into it 
and sent out two engineers to explain it to me. They could explain it 
correctly, and then tried the sales-guy to cover it up and say it worked 
well enough for others and THAT is when I decided they where running an 
uphill game. Anyway, I think some engineers learned the hard way that 
you need to adjust the design as you change critical parts of the design.

Even a "simple" setup for testing can be quite revealing.

Cheers,
Magnus

On 06/10/2017 09:50 PM, Bob kb8tq wrote:
> Hi
>
> The next issue is that “noise” has a pretty broad definition in this case.
> If you are looking at set point, it also would include temperature drift and
> aging. Neither one seem to show up on the standard MCU ADC data sheets :)
> It can even be a bit difficult to find them on some (but certainly not all)
> standalone ADC specs.
>
> Next layer to the onion:
>
> If we want to hold the oven at some temperature +/- 0.1 C, the control loop
> needs to go from full on to full off over that range. For grins, let’s assume
> that the output is a 16 bit DAC. You will map (somehow) the full range of the
> output into a 0.2 C input range.
>
> If you have a P only controller, the output will step at the granularity of the
> ADC over the 0.2C range. If you have 4 extra bits, you will get 16 x 2 = 32
> output levels. That’s not really making the 16 bit DAC earn it’s living.
>
> A PI controller can (at least theoretically) fill in all of the states of the 16 bit DAC regardless
> of the input granularity. If the P is very small and the I is very large it will
> do this fairly seamlessly. In the example above setting P to  < 1/ 2^11 would
> likely do the trick. This all may (or may not) let you hit the P value (or P to I ratio)
> you desire.
>
> Why does the output DAC matter? Each time the DAC steps, the current
> in the heater changes. That power change times the thermal resistance gives
> you a temperature step. It is yet another source of “noise” to the crystal.
> Minimizing thermal noise is one of the many things that gets you better ADEV.
>
> Bob
>
>> On Jun 10, 2017, at 3:24 PM, Chris Albertson <albertson.chris at gmail.com> wrote:
>>
>> On Sat, Jun 10, 2017 at 11:33 AM, Magnus Danielson <
>> magnus at rubidium.dyndns.org> wrote:
>>
>>> Hi,
>>>
>>> I was about to make this very point myself. The resolution of the ADC
>>> needs to be higher than the limit you try to achieve. There is several ways
>>> to reason about it, but one is that the system is a bit slugish you want to
>>> have higher resolution in order to react of changes before they overshot
>>> the limits you want to keep. Another benefit is that you get away from the
>>> bang-bang behavior you get when having too few bits.
>>>
>>> For an oven you can however cheat some by not requiring linearity in the
>>> "too cold" region of temperature. You do want some linearity as you start
>>> to come into the right range in order to slow down the heating in order not
>>> to do a big overshot.
>>>
>>> I have seen a little too much cases where there been too few bits both on
>>> ADC and DAC sides. Some of it you can overcome, but it runs into trouble.
>>> Get good dynamics, it makes the rest of the design easier.
>>>
>>
>>
>>
>>
>> OK, following the advice both above and below.  Let's try some real-world
>> numbers...
>>
>> Lets say my goal is regulation within 0.1C.  After filtering I have 10
>> "good" bits in my ADC.  That is 1024 counts.   My set point is S.
>>
>> I scale the ADC so that 0 == (S - 0.5) and 1023 == (S + 0.5)    This means
>> that each ADC count is 0.001 degree C and within the 0.1C range there are
>> 100 ADC counts.
>>
>> But what if there are only 8 good bits after filtering   The each count is
>> 0.004 degree C and there are 25 counts within the 0.1C range.
>>
>> The uP's ADC is nominally 12 bits.   Getting 10 "good" noise free bits
>> might be asking to much but 8-bits is pretty reasonable.
>>
>>
>>
>>
>>
>>>
>>> Cheers,
>>> Magnus
>>>
>>> On 06/07/2017 08:32 PM, Bob kb8tq wrote:
>>>
>>>> Hi
>>>>
>>>> There is a gotcha with the initial assumption: You want the loop to be
>>>> *quiet* at a level well below 0.1C. If it is bouncing around that much,
>>>> the second order (rate defendant) tempco of a normal crystal will
>>>> become a pretty major issue.
>>>>
>>>> Simple rule of thumb - add at least two bits past whatever the target is.
>>>> More or less, if you *are* after 0.1C and that comes out to 6 bits, you
>>>> need
>>>> eight solid bits to get things to work properly.
>>>>
>>>
>> --
>>
>> Chris Albertson
>> Redondo Beach, California
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