[time-nuts] Single ended or differential input to TDC chip
bruce.griffiths at xtra.co.nz
Mon Mar 27 16:25:26 EDT 2017
Differential inputs, either LVDS or PECL compatible, together with a fast single supply comparator for the CMOS to PECL to LVDS/differential PECL would be the conservative approach. Ultra fast comparators with aaa delay belowwww 2ns are readddddddddilyy available.
Alternatively a CMOS to LVDS converter like:
could be used.
There are commercial TDCs that claim similar resolution that use CMOS inputs.
One could provide both CMOS and differential inputs so that if the CMOS inputs prove problematic one could just use the differential inputs.
> On 28 March 2017 at 05:05 Attila Kinali <attila at kinali.ch> wrote:
> We (the group I am with and a group at TU Vienna) are currently designing
> an ASIC (digital 65nm process) that will contain a TDC part. The TDC will
> be a simple delay line TDC design using differential buffers, which we
> expect to give us something in the order of 20ps of resolution (hopefully
> better, but we will not know until we get post-layout simulation data).
> We are loosely following the design CERN came up with for their new TDC chip.
> Now, the TDC expects a differential input, but the system gets single-ended
> pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not
> fixed yet, ie can be freely choosen). I can either convert these single-ended
> signals into differential off-chip or on-chip. Unfortunately, I lack knowledge
> and experience to judge either approach. The issues I see are:
> * Single-ended input in a chip might lead to shifting ground potential
> on the chip and thus to measurment jitter.
> * There are different architectures to preform the single-ended to differential
> conversion on-chip, but I have no clue which one to choose or even how
> to judge them without extensive simulations for which we do not have the
> time, know-how and probably not even the tools.
> * Conversion to differential off-chip means another component off-chip
> that might introduce additional delay uncertainty (our application is
> very sensitive to that) and an unknown amount of jitter.
> My google foo has been so far not strong enough to find answers to these
> I would appreciate if someone could give me some hints in this matter
> or tell me where I could find appropriate literature and maybe even
> tell me whether I am missing anything.
> Thanks in advance
> Attila Kinali
>  https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf
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