[time-nuts] Single ended or differential input to TDC chip
magnus at rubidium.dyndns.org
Mon Mar 27 17:36:32 EDT 2017
On 03/27/2017 06:05 PM, Attila Kinali wrote:
> We (the group I am with and a group at TU Vienna) are currently designing
> an ASIC (digital 65nm process) that will contain a TDC part. The TDC will
> be a simple delay line TDC design using differential buffers, which we
> expect to give us something in the order of 20ps of resolution (hopefully
> better, but we will not know until we get post-layout simulation data).
> We are loosely following the design CERN came up with for their new TDC chip.
> Now, the TDC expects a differential input, but the system gets single-ended
> pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not
> fixed yet, ie can be freely choosen). I can either convert these single-ended
> signals into differential off-chip or on-chip. Unfortunately, I lack knowledge
> and experience to judge either approach. The issues I see are:
> * Single-ended input in a chip might lead to shifting ground potential
> on the chip and thus to measurment jitter.
> * There are different architectures to preform the single-ended to differential
> conversion on-chip, but I have no clue which one to choose or even how
> to judge them without extensive simulations for which we do not have the
> time, know-how and probably not even the tools.
> * Conversion to differential off-chip means another component off-chip
> that might introduce additional delay uncertainty (our application is
> very sensitive to that) and an unknown amount of jitter.
> My google foo has been so far not strong enough to find answers to these
> I would appreciate if someone could give me some hints in this matter
> or tell me where I could find appropriate literature and maybe even
> tell me whether I am missing anything.
There is benefit of going diffrential over the chip border, and there is
plenty of examples where it has been used for great benefit. Make sure
to keep ground attached to neighbor pins/balls. When we run 10 Gb/s with
low jitter (7 ps RMS max), then we need and use differential signals.
Single-mode to differential mode conversion can be done off-chip if
needed, and it may suffice with very simple setups, allowing for passive
What you might want to look at iis if you have a good CMRR of your
differential input or if you should have a inputstage to get better margin.
More information about the time-nuts