[time-nuts] Single ended or differential input to TDC chip

Gerhard Hoffmann dk4xp at arcor.de
Mon Mar 27 20:00:11 EDT 2017


Hi, Attila!

Somewhere you'll have to produce sharp differential edges and this
semi-analogue stuff is probably hard on a chip shared with thousands of
other gates and a digital process. Going differentially into the chip will
reduce the effects of ground bounce etc a lot.

This is what you can expect from an ADCMP580 on a homebrew
board and soldered-in semi rigid cable:
< 
https://www.flickr.com/photos/137684711@N07/33305853110/in/album-72157662535945536/ 
 >

Some will cry: eeek - a comparator, and an ECL or CML one at that, but 
in the end
it is just a differential amplifier like that Wenzel design, made by 
people who
know their SiGe process.

If you have a slowly rising source, you'll need multi-stage slope 
amplification
and low pass filtering in Collins style anyway which will be safer to do 
off-chip.

If you can specify the interface, go for something speedy, then
the guys who do the the signal source have the hard time and
can be pointed at.  :-))

regards, Gerhard



Am 27.03.2017 um 18:05 schrieb Attila Kinali:
> Hi,
>
> We (the group I am with and a group at TU Vienna) are currently designing
> an ASIC (digital 65nm process) that will contain a TDC part. The TDC will
> be a simple delay line TDC design using differential buffers, which we
> expect to give us something in the order of 20ps of resolution (hopefully
> better, but we will not know until we get post-layout simulation data).
> We are loosely following the design CERN came up with for their new TDC chip[1].
>
>
> Now, the TDC expects a differential input, but the system gets single-ended
> pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not
> fixed yet, ie can be freely choosen). I can either convert these single-ended
> signals into differential off-chip or on-chip. Unfortunately, I lack knowledge
> and experience to judge either approach. The issues I see are:
>
> * Single-ended input in a chip might lead to shifting ground potential
>    on the chip and thus to measurment jitter.
> * There are different architectures to preform the single-ended to differential
>    conversion on-chip, but I have no clue which one to choose or even how
>    to judge them without extensive simulations for which we do not have the
>    time, know-how and probably not even the tools.
> * Conversion to differential off-chip means another component off-chip
>    that might introduce additional delay uncertainty (our application is
>    very sensitive to that) and an unknown amount of jitter.
>
> My google foo has been so far not strong enough to find answers to these
> questions.
>
> I would appreciate if someone could give me some hints in this matter
> or tell me where I could find appropriate literature and maybe even
> tell me whether I am missing anything.
>
> Thanks in advance
>
> 				Attila Kinali
>
> [1] https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf





More information about the time-nuts mailing list