[time-nuts] femtosecond jitter

John Larkin jjlarkin at highlandtechnology.com
Sat Apr 14 12:45:10 EDT 2018

Hi, Magnus,

We did a little PC board that has two Analog Devices CML comparators 
that feed the flop.


An external DAC tweaks the VBIAS voltage to slew the edge times across 
one another, and an external ADC looks at the averaged flop outputs. The 
jitter noise floor is probably dominated by the test signals, not the 
flop under test. We considered something like a micrometer-driven 
differential trombone line... note that 1 fs is one PPM of a nanosecond, 
how far light travels in 12 micro-inches.

The quantization is probably DAC resolution. The step function is just 
the integral of the histogram.

This is going into a test set that needs maybe 1 ps RMS noise floor, so 
this flop is hugely better than what we need. It's a big deal to set 
this up, so I don't think we'll do any more measurements.

As a bang-bang phase detector, with some lowpass filtering in the loop, 
this flop would have a noise floor in the attosecond range. You're 
right, temperature will dominate low-frequency noise, and not just in 
the flop.


On 4/14/2018 5:59 AM, Magnus Danielson wrote:
> John,
> How where these measurements done?
> Also, it looks like you have a systematic component in there, about 80
> fs guestimating from the plot creating essentially two tracks up the
> slope that is the tell-tale of a sinuoid phase modulation of some source.
> Considering the temperature stability that you nicely plotted as a
> quadratic shape, it seems like a good thermal stability is needed, which
> comes as no big chock.
> Can do you do a longer measurement and accumulate the data in a
> 2D-histogram fashion? That is count occurrences for the amplitude/time
> position and then color code it accordingly? That have proved to be a
> good tool for analysis.
> Cheers,
> Magnus
> On 04/13/2018 05:54 PM, John Larkin wrote:
>> If you walk the differential data and clock inputs of an NB7V52  CML
>> flipflop across one another in time, the equivalent jitter is below 20
>> fs RMS. That's what we're measuring, but our test rig may well dominate
>> the jitter, so the flop is probably better.
>> We're using this to test the jitter of some of our timing products, with
>> 1/10 the noise floor and 1e-4 times the cost of other ways to do it.
>> https://www.dropbox.com/s/1i2yz7otty94o9l/NB7_Jitter_1.jpg?raw=1
>> https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1
>> https://www.dropbox.com/s/tpphhi79yxgzy34/NB7_tc.jpg?raw=1
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John Larkin, President
Highland Technology, Inc
18 Otis Street
San Francisco, CA 94103

phone 415 551-1700   fax 551-5129
jjlarkin at highlandtechnology.com

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