[time-nuts] femtosecond jitter

John Larkin jjlarkin at highlandtechnology.com
Mon Apr 16 11:31:17 EDT 2018



On 4/15/2018 2:17 PM, Magnus Danielson wrote:
> Hi,
>
> On 04/14/2018 06:45 PM, John Larkin wrote:
>> Hi, Magnus,
>>
>> We did a little PC board that has two Analog Devices CML comparators
>> that feed the flop.
>>
>>    https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
>>
>> An external DAC tweaks the VBIAS voltage to slew the edge times across
>> one another, and an external ADC looks at the averaged flop outputs. The
>> jitter noise floor is probably dominated by the test signals, not the
>> flop under test.
> Ah, thanks. Much clearer now!
>
> You more tweak the voltage than actual timing, it's the slope property
> that does the timing, but interesting never the less.

Downstream of the comparators, all the flop sees is time... not voltage 
shift. We used a sampling scope to calibrate the picoseconds-per-volt 
slope of the voltage input from the DAC.


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John Larkin, President
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