attila at kinali.ch
Mon Jan 22 13:35:42 EST 2018
On Mon, 22 Jan 2018 08:18:29 -0600
"Chris Caudle" <chris at chriscaudle.org> wrote:
> The DSP loop filter gives a really wide range of loop bandwidth, down to
> fractional Hz for some parts. Using a DDS for the VCO gives a lot of
> flexibility in output frequency selection, but means that there can be
> problems with spurs. Part of the SiLabs secret sauce is supposed to
> reduce spurs compared to a simpler NCO implementation, but I don't think
> you can eliminate spurs entirely with any kind of DDS based design.
The secret sauce is not so secret, actually. It's just how you
build a higher order delta-sigma modulator. Most PLL implementations
still use a 1st-order modulator, with the well known spur problem
(they arise from the "idle-tone" problem in delta-sigma modulators)
The "low-spur" fractional PLLs use a 2nd or 3rd order modulator.
There has been some research in the last decade or so on how to
reduce those spurs further (mostly using even higher order and some
times using tricks like actively introducing errors to spread the
spurs) and most of it can be found online on IEEE and the like.
For a gentle introduction, have a look at Schreier, Pavan and Teme's
book "Understanding Delta Sigma Data Converters."
I find the idea of using two cascaded control loops neat. It helps
to control erros (aka noise) contributed by the second (inner) loop.
However, how this reduces suceptibility to vibration, I am not entirely sure.
The reason why most people do not do this is easily explained: it's more
difficult to get a stable system with nested loops, as the conditions
for stability becomes more complex than with just a standard, straight
forward PID loop.
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the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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