[time-nuts] Slightly OT: interest in a four-output, ultra-low jitter, synthesizer block?
John Ackermann N8UR
jra at febo.com
Thu Jan 25 19:45:39 UTC 2018
Hi Bill --
I should have been more clear: this design will be for a simple case:
one reference clock input, four outputs. The chip can do all sorts of
fancy tricks, but I'm looking for a source of four low jitter outputs
derived from a 10 MHz external reference (not using crystal or on-board
oscillator). Many of the pins are unused in that configuration.
I'm not looking to make a universal carrier for the chip, but to meet
what I suspect is a common time-nut/ham radio desire for a clean
multi-channel synthesizer.
On 01/25/2018 02:02 PM, wb6bnq wrote:
> Hi John,
>
> After looking at the data sheet, it seems way more involved then just
> making a carrier board for it. Besides the power supply requirements,
> various design selections would dictate different circuit layouts for
> different purposes. Even trying to do a general purpose application
> would possibly require having several different output configurations
> and possibly a couple of input configurations as well. That would imply
> a rather detailed PCB and that chip package style is a serious pain in
> the ass for [what amounts to] hobbyists. So it would seem the logical
> course would be to do serious design application and see if an in-house
> component mounting job would be feasible.
>
> I notice that the data sheet says the jitter specs are only best when
> using The internal crystal oscillator frequency between 48 and 54 MHz.
> It was unclear to me that the same would apply to using the non-crystal
> inputs.
>
> Perhaps you could indicate what you are attempting to do with it and how
> you are going to accomplish your goals ?
>
> 73....Bill....WB6BNQ
>
>
> John Ackermann N8UR wrote:
>
>> After the recent discussion about Silicon Labs clock generators, I
>> looked at their Si5340A part and think it will be useful for a ham
>> radio project I'm working on. While it can do other things, for my
>> use it would use a 10 MHz input clock and generate 4 independent
>> outputs in the range of 100 kHz to 1028 MHz. Its jitter is <100fs,
>> which translates to "not bad" phase noise. Here's the data sheet if
>> you're interested:
>>
>> http://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
>>
>>
>> The challenge is that the chip is a 7x7 mm 44-QFN package and really
>> wants to be put on a six-layer circuit board. That's doable, but
>> challenging, for home assembly.
>>
>> Rather than designing the chip into a larger circuit board, I'm
>> thinking of doing a small "carrier" board that would include just the
>> chip and critical bypass caps and have headers to plug into the main
>> board. Then, you could just drop the carrier into a project-specific
>> board and not have to worry about the complex layout and mounting. I
>> have a contract manufacturer who can build these up, if there's enough
>> quantity to justify the setup cost.
>>
>> If you'd be interested acquiring in one or more of these, please drop
>> me a line off-list (jra at febo dot com). I don't think this will be
>> a TAPR project, but if there's enough interest to build 25 of these
>> carriers, I can probably make that happen. And remember -- this is
>> just the chip; you'll need to provide the rest of the circuit.
>>
>> John
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