[time-nuts] Slightly OT: interest in a four-output, > ultra-low jitter, synthesizer block?

Joseph Gwinn joegwinn at comcast.net
Fri Jan 26 03:17:57 UTC 2018


On Thu, 25 Jan 2018 21:13:44 -0500, time-nuts-request at febo.com wrote:
> 
> Message: 2
> Date: Thu, 25 Jan 2018 16:16:59 -0500
> From: John Ackermann N8UR <jra at febo.com>
> To: time-nuts at febo.com
> Subject: Re: [time-nuts] Slightly OT: interest in a four-output,
> 	ultra-low jitter, synthesizer block?
> Message-ID: <df6ea5f9-50b4-ecef-7eae-a7bc391fb03b at febo.com>
> Content-Type: text/plain; charset=utf-8; format=flowed
> 
> Yes, I was planning to include bypasses, and I've been convinced to put 
> at least the 1.8V regulator on the board as well.  And to think about 
> the interconnects.

What I've seen widely done in circuits requiring low phase noise is to 
have a cascade of regulators, all but the last one (that feeds the RF 
component in question) beings switchers of different switching 
frequency, with simple low-pass filters between the regulators, and 
between the last regulator and the RF component being powered.
  Between the filtration due to the regulators and that due to the 
LPFs, one can achieve very large ripple and noise attenuations.


Joe Gwinn


 
> Adding the crystal does make the layout more complex -- they put a 
> ground pour on its own layer underneath it, and I think (but am not 
> sure) that the connections complicate selecting an external oscillator. 
> I'll look into the pain tradeoff.
> 
> On 01/25/2018 04:08 PM, Robert LaJeunesse wrote:
>> John, I appreciate your minimalist goal, but I'll second Bill's 
>> section about including the power supply voltage regulator and 
>> bypassing. Finding a good regulator with wideband line 
>> regulation/rejection could prove a real search, and such a fast chip 
>> as the Si5340 will need excellent broadband supply bypassing. So 
>> keep these key components tight to the chip, on the same PCB 
>> obviously. The need for a 4- to 6-layer board screams "keep critical 
>> loops tight"! FYI a regulator (of needed RF performance) producing 
>> 3.3V for VDDA will likely have an absolute max input voltage of 6V 
>> or so. Having a 5V supply requirement will not be a serious 
>> limitation of the overall system design. I'm sure you know the 1.8V 
>> supply regulators should not be fed from VDDA (3.3V), but I'll 
>> mention it anyway.
>> 
>> With that much on the PCB adding a small crystal can't add 
>> significantly to the cost, so why not? It allows R&D of the chip and 
>> outputs before having to hook up one's 10MHz reference. As such 
>> crystal quality / stability / etc. are of little concern - just size 
>> & cost.
>> 
>> I also like the previous suggestion of castellated connections on 
>> the board edge - easy to solder to a board and easy to solder wires 
>> to. If you make the castellations on 0.1" (or 2mm) centers then it 
>> becomes possible to use common header pins as well. Just keeping 
>> your options open there.
>> 
>> Bob L.
>> 
>>> Sent: Thursday, January 25, 2018 at 3:23 PM
>>> From: "John Ackermann N8UR" <jra at febo.com>
>>> To: time-nuts at febo.com
>>> Subject: Re: [time-nuts] Slightly OT: interest in a four-output, 
>>> ultra-low jitter, synthesizer block?
>>> 
>>> Hi Bill --
>>> 
>>> And that's exactly what I *don't* want to do. :-)  The reason is that I
>>> have several different projects in mind (and everyone else will have
>>> their own requirements) and only want to deal with the difficult package
>>> once.
>>> 
>>> The idea is to make a minimal carrier to deal with the tiny part and
>>> six-layer board.  Then all the ancillary stuff (including the MCU that's
>>> needed to program the chip) goes onto the board designed for that
>>> project.  This isn't intended to be a finished product, just a building
>>> block.
>>> 
>>> 73,
>>> John
>>> ----
>>> On 01/25/2018 03:12 PM, wb6bnq wrote:
>>>> Hi John,
>>>> 
>>>> Thanks for the response.  Here is my 2 cents:
>>>> 
>>>> Well, due to the level of difficulty in chip mounting, I would prefer to
>>>> see a complete project. I.E., power supply for a single input of 12
>>>> volts and regulators the necessary chip values, proper input protection
>>>> for the 10 MHz input level and single ended outputs of the appropriate
>>>> levels (I am assuming more than 3 volts) or an amplifier stage for
>>>> arriving at such.  Equally have RF connectors (SMA would be good) on the
>>>> board perhaps.
>>>> 
>>>> Of course as cheap as possible, hi hi.  A carrier board arrangement
>>>> would be useless to me.  My application would be to provide signals for
>>>> things like my Quicksilver SDR receiver, among other uses.
>>>> 
>>>> If you are interested, I can show you a nice little ABS (I think) box
>>>> that has EMI built-in that I used for a project that should be more than
>>>> large enough for your needs.
>>>> 
>>>> Thanks for reading,
>>>> 
>>>> 73....Bill....WB6BNQ
>>>> 
>>>> 
>>>> John Ackermann N8UR wrote:
>>>> 
>>>>> Hi Bill --
>>>>> 
>>>>> I should have been more clear: this design will be for a simple case:
>>>>> one reference clock input, four outputs.  The chip can do all sorts of
>>>>> fancy tricks, but I'm looking for a source of four low jitter outputs
>>>>> derived from a 10 MHz external reference (not using crystal or
>>>>> on-board oscillator).  Many of the pins are unused in that 
>>>>> configuration.
>>>>> 
>>>>> I'm not looking to make a universal carrier for the chip, but to meet
>>>>> what I suspect is a common time-nut/ham radio desire for a clean
>>>>> multi-channel synthesizer.
>>>>> 
>>>>> On 01/25/2018 02:02 PM, wb6bnq wrote:
>>>>> 
>>>>>> Hi John,
>>>>>> 
>>>>>> After looking at the data sheet, it seems way more involved then just
>>>>>> making a carrier board for it.  Besides the power supply
>>>>>> requirements, various design selections would dictate different
>>>>>> circuit layouts for different purposes.  Even trying to do a general
>>>>>> purpose application would possibly require having several different
>>>>>> output configurations and possibly a couple of input configurations
>>>>>> as well.  That would imply a rather detailed PCB and that chip
>>>>>> package style is a serious pain in the ass for [what amounts to]
>>>>>> hobbyists.  So it would seem the logical course would be to do
>>>>>> serious design application and see if an in-house component mounting
>>>>>> job would be feasible.
>>>>>> 
>>>>>> I notice that the data sheet says the jitter specs are only best when
>>>>>> using The internal crystal oscillator frequency between 48 and 54
>>>>>> MHz. It was unclear to me that the same would apply to using the
>>>>>> non-crystal inputs.
>>>>>> 
>>>>>> Perhaps you could indicate what you are attempting to do with it and
>>>>>> how you are going to accomplish your goals ?
>>>>>> 
>>>>>> 73....Bill....WB6BNQ
>>>>>> 
>>>>>> 
>>>>>> John Ackermann N8UR wrote:
>>>>>> 
>>>>>>> After the recent discussion about Silicon Labs clock generators, I
>>>>>>> looked at their Si5340A part and think it will be useful for a ham
>>>>>>> radio project I'm working on.  While it can do other things, for my
>>>>>>> use it would use a 10 MHz input clock and generate 4 independent
>>>>>>> outputs in the range of 100 kHz to 1028 MHz.  Its jitter is <100fs,
>>>>>>> which translates to "not bad" phase noise.  Here's the data sheet if
>>>>>>> you're interested:
>>>>>>> 
>>>>>>> 
http://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
>>>>>>> 
>>>>>>> 
>>>>>>> The challenge is that the chip is a 7x7 mm 44-QFN package and really
>>>>>>> wants to be put on a six-layer circuit board.  That's doable, but
>>>>>>> challenging, for home assembly.
>>>>>>> 
>>>>>>> Rather than designing the chip into a larger circuit board, I'm
>>>>>>> thinking of doing a small "carrier" board that would include just
>>>>>>> the chip and critical bypass caps and have headers to plug into the
>>>>>>> main board. Then, you could just drop the carrier into a
>>>>>>> project-specific board and not have to worry about the complex
>>>>>>> layout and mounting.  I have a contract manufacturer who can build
>>>>>>> these up, if there's enough quantity to justify the setup cost.
>>>>>>> 
>>>>>>> If you'd be interested acquiring in one or more of these, please
>>>>>>> drop me a line off-list (jra at febo dot com).  I don't think this
>>>>>>> will be a TAPR project, but if there's enough interest to build 25
>>>>>>> of these carriers, I can probably make that happen.  And remember --
>>>>>>> this is just the chip; you'll need to provide the rest of the circuit.
>>>>>>> 
>>>>>>> John
>>>>>>> _______________________________________________
> 
> End of time-nuts Digest, Vol 162, Issue 38
> ******************************************



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