[time-nuts] HP 5065A A1 replacement with DDS
Dana Whitlow
k8yumdoober at gmail.com
Mon Jun 25 09:05:49 EDT 2018
A useful hardware demonstration of DDS phase truncation is to do step a DDS
through a long
series of frequencies at a relatively low stepping rate, and view the
output with an FFT-based
(real-time) spectrum analyzer set for spectrogram display. Watch this for
a while and it becomes
quite easy to reach a practical understanding of what's going on and how
the spurs behave.
Note that to avoid confusion from aliasing products, it is a good idea to
constrain the range of
frequencies swept to the first Nyquist zone (zero to < 1/2 the DDS clock
frequency).
There's a fairly simple regularity in the spur behavior which is not
particularly obvious from
looking at equations and tables (at least, not at my math skill level), but
which jumps out at
you in the spectrogram display (or even without the spectrogram).
Dana
On Mon, Jun 25, 2018 at 7:38 AM, jimlux <jimlux at earthlink.net> wrote:
> On 6/24/18 2:05 PM, Hal Murray wrote:
>
>>
>> Poul-Henning Kamp said:
>>
>>> That's one of the reason I went with Bo's DDS (32bit0 instead of the eBay
>>> modules (20-24 bit). Higher resolution mitigates the spur problem at
>>> least a
>>> little bit.
>>>
>>
>> I think it also moves the spurs closer in. But maybe if they are small
>> enough
>> they get lost in the normal noise.
>>
>> Does anybody have a handy formula for the spurs given the parameters for
>> a DDS?
>>
>
>
> There isn't one.. <grin>
>
> The spur size and location is more determined by "how many loops through
> the cosine table til you wind up back at zero" which gets down to the phase
> quantization - or the cosine table size
>
> Think of a cosine table that's 16 elements long (i.e. a 4 bit phase).
>
> If the output frequency is fclk*8/16, your DDS puts out entry 0 and entry
> 8, and repeats
> If the output frequency is fclk*2/16, your DDS puts out entry
> 0,2,4,6,8,10,12,14,0,2,4,6
>
> If the output frequency is fclk*3/16, your DDS puts out 0,
> 3,6,9,12,15,2,5,... and it takes a few cycles to repeat around
>
> If the output frequency is fclk*2.5/16, your DDS puts out
> 0,2,5,7,10,12,15,1,4,6,9,11,14,0,3, etc.
>
> these all have very different spur patterns.
>
>
>
>> I've occasionally thought of writing code to generate the output of a DDS
>> and
>> run it through a FFT. I haven't figured out how much memory that would
>> need,
>> or rather how wide a DDS I could simulate with the memory I have. A 20
>> bit
>> accumulator repeats after a million cycles. At 8 bytes/sample that's 8
>> megabytes which I can do. (Round down if FFT needs another copy.)
>>
>
> That is, in fact how people do it.
>
>
>
>> We are only interested in the close-in area, so old brute-force
>> calculations
>> maybe fast enough.
>>
>>
>>
>>
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