[time-nuts] 1 pps sync'ing

Chris Caudle chris at chriscaudle.org
Fri Jun 29 10:20:04 EDT 2018


Sorry, got distracted part way through this email and left out an
important section:

On Fri, June 29, 2018 8:51 am, Chris Caudle wrote:
> 100MHz tuneable oscillator -> divide by 10 -> 10MHz
> 10MHz -> divide by 10M -> 1Hz
> ...data input of a D flip-flop, clocked by the 100MHz,
> and now the 100MHz, 10MHz, and 1Hz edges
> are offset only by the delay through the flip-flop.

After you have three clock signals synchronized to each other, you still
have to steer to line up with your input PPS signal.  You will have to
build a PLL to compare your generated 1Hz clock and the input PPS and
steer  the 100MHz oscillator to keep them lined up.  You would also want
some logic to control the reset on the dividers to get the signals started
out close to lined up with the input PPS or it might take a very long time
to achieve lock.

That is where having something like the Analog Devices part (or similar
Silicon Labs, Microsemi, etc.) are useful, they save the problems of
designing the digital PLL.

-- 
Chris Caudle







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