[time-nuts] How to properly simulate PLLs?

[Bob Darby]

http://www.aholme.co.uk/Frac2/Simulate.htm

might be useful.

bob

-----Original Message-----
From: time-nuts <time-nuts-bounces at febo.com> On Behalf Of Attila Kinali
Sent: Wednesday, March 7, 2018 11:43 AM
To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
Subject: [time-nuts] How to properly simulate PLLs?

Hi,

I have a small side task, where I need to design a PLL system As it is a bit non-conventional, I am not confident that my pen and paper analysis is correct and the usuall tool I use (Analog's ADPLLsim) doesn't cover it. So my first thought was to use spice to simulate the loop. But I am not sure how the non-linear effects of the PLL, the divider chains etc affect the whole system and whether a spice simulation (which would use a linear approximation of a few components) would model the system faithfully. Not to mention that this would be only valid simulation of the locked state and anything that involves the PLL being unlocked (initial lock in process, large phase and frequency jumps that cause unlocks) cannot be handled at all. Neither would it give me a proper estimate of the noise propagation through the system.

So, is there any canonical way how to simulate PLLs?
If yes, what should I read? (My google foo didn't return anything helpful).

Thanks in advance

			Attila Kinali

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