[time-nuts] lecture on PLL and phase noise and verilog

[Azelio Boriani]

Maybe that such a technique can be applied to the simulation of
counters and interpolators, an actual topic on this list.

On Mon, May 14, 2018 at 2:47 PM, jimlux <jimlux at earthlink.net> wrote:
> If you're in California southern Central Coast area (Ventura, Santa Barbara,
> Thousand Oaks, etc.) the local IEEE chapter is sponsoring a talk on phase
> noise and Verilog
>
> https://events.vtools.ieee.org/m/172159
>
> PLL'S AND PHASE NOISE MODELING IN VERILOG
> Verilog is the accepted language of choice for modeling and simulating
> digital designs. For analog blocks the tool choice is a low level circuit
> simulator like HSPICE or Spectre. For PLL’s a common misconception is that
> you can use Verilog to model a PLL if you don't care about accuracy, but if
> you do care about precision, you'll need an analog circuit simulator like
> HSPICE or Spectre. Various options like Verilog-A and Verilog-AMS are
> attempts to achieve the best of both worlds, but in this talk, we propose
> that the tool of choice for modeling and studying PLL’s and is plain
> “digital” Verilog. It's the right tool, but almost always used the wrong way
> for modeling PLL's. Understanding how the underlying simulation engine in
> Verilog works enables us to set up our models in a very precise, yet very
> simple manner. The efficiency and speed of Verilog allows us to literally
> watch our PLL designs come alive in the time domain with timing accuracy
> that can't be achieved in an analog circuit simulator. Watching designs
> operate in the time domain crystalizes our understanding of them, and
> enables us to study and quantify transient and other non-linear phenomena.
>
>
> Biography:
>
> Greg Warwar received a master’s degree in electrical engineering from Rice
> University in 1989. Following graduation, he joined Texas Instruments in
> Dallas, TX as a member of the technical staff where he worked on ΣΔ analog
> to digital converters for precision audio applications. In 1992, he joined
> Vitesse Semiconductor in Camarillo, CA where he worked for 23 years on high
> speed serial communications IC’s, focusing on many areas of analog and
> mixed-signal design including VCO’s, phase locked loops, clock recovery,
> frequency synthesizers, and adaptive equalization. Since 2015, Greg has been
> a principal engineer in the mixed-signal ASICs design group at Teradyne,
> Inc. in Agoura Hills, CA. Greg holds six U.S. patents in the area of CMOS
> mixed-signal IC design.
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.